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-rw-r--r--2004/n/fpga/src/decodisa/bch_decodisa.vhd140
1 files changed, 77 insertions, 63 deletions
diff --git a/2004/n/fpga/src/decodisa/bch_decodisa.vhd b/2004/n/fpga/src/decodisa/bch_decodisa.vhd
index 91a6bc9..be1d071 100644
--- a/2004/n/fpga/src/decodisa/bch_decodisa.vhd
+++ b/2004/n/fpga/src/decodisa/bch_decodisa.vhd
@@ -1,63 +1,77 @@
-
--- VHDL Test Bench Created from source file decodisa.vhd -- 02:25:56 03/17/2004
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-ENTITY decodisa_bch IS
-END decodisa_bch;
-
-ARCHITECTURE behavior OF decodisa_bch IS
-
- COMPONENT decodisa
- PORT(
- adr_bus : IN std_logic_vector(23 downto 0);
- AEN : IN std_logic;
- IOR : IN std_logic;
- IOW : IN std_logic;
- cs : OUT std_logic_vector(255 downto 0);
- rw : OUT std_logic;
- clk : OUT std_logic
- );
- END COMPONENT;
-
- SIGNAL adr_bus : std_logic_vector(23 downto 0):=(others => '0');
- SIGNAL AEN : std_logic:='0';
- SIGNAL IORosc : std_logic:='0';
- SIGNAL IOWosc : std_logic:='0';
- SIGNAL IOR : std_logic:='0';
- SIGNAL IOW : std_logic:='0';
- SIGNAL cs : std_logic_vector(255 downto 0);
- SIGNAL rw : std_logic;
- SIGNAL clk : std_logic;
-
-BEGIN
-
- uut: decodisa PORT MAP(
- adr_bus => adr_bus,
- AEN => AEN,
- IOR => IOR,
- IOW => IOW,
- cs => cs,
- rw => rw,
- clk => clk
- );
-
-adr_bus <= conv_std_logic_vector(unsigned(adr_bus) + 1 , 24) after 120 ns;
-aen<= not aen after 13000 ns;
-iorosc<= not iorosc after 7000 ns;
-iowosc<= not iowosc after 5000 ns;
-
-ior<=not(iorosc and not aen);
-iow<=not(iowosc and not aen);
-
-END;
+-- bch_decodeur4.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Test du decodeur4.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+
+entity bch_decodeur4 is
+end bch_decodeur4;
+
+architecture sim1 of bch_decodeur4 is
+
+ component decodeur4
+ generic (
+ -- adresses des différents registres du module.
+ A_REG0 : T_ADDRESS;
+ A_REG1 : T_ADDRESS;
+ A_REG2 : T_ADDRESS;
+ A_REG3 : T_ADDRESS
+ -- si autre choses à déclarer...
+ );
+ port (
+ -- TODO : utile la clock ?
+ --clk : in std_logic;
+ bus_address : in T_ADDRESS;
+ enable0 : out std_logic;
+ enable1 : out std_logic;
+ enable2 : out std_logic;
+ enable3 : out std_logic
+ );
+ end component;
+
+ -- définiton des signaux
+ --signal clk : std_logic := '0';
+ signal bus_address : T_ADDRESS;
+ signal enable0 : std_logic;
+ signal enable1 : std_logic;
+ signal enable2 : std_logic;
+ signal enable3 : std_logic;
+
+begin
+ U1 : decodeur4
+ generic map (
+ -- Définition des addresses.
+ A_REG0 => A_IO1_REG_DATA,
+ A_REG1 => A_IO1_REG_DIRECTION,
+ A_REG2 => A_IO1_REG_INTERRUPT_MASK,
+ A_REG3 => A_IO1_READ_OUTPUT
+ )
+ port map (
+ bus_address => bus_address,
+ enable0 => enable0,
+ enable1 => enable1,
+ enable2 => enable2,
+ enable3 => enable3
+ );
+
+ --clk <= not clk after (CK_PERIOD/2);
+ bus_address <= A_IO1_REG_DIRECTION,
+ A_IO1_READ_OUTPUT after 3*CK_PERIOD,
+ A_IO1_REG_INTERRUPT_MASK after 5*CK_PERIOD,
+ A_IO1_REG_DATA after 7*CK_PERIOD;
+end sim1;
+
+
+configuration cf1_bch_decodeur4 of bch_decodeur4 is
+ for sim1
+ for all : decodeur4 use entity work.decodeur4(RTL); end for;
+ end for;
+end cf1_bch_decodeur4;
+