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authorprot2004-02-26 10:47:33 +0000
committerprot2004-02-26 10:47:33 +0000
commit7815edf8cffb20a4a33199599a35bb8c107b16d1 (patch)
tree3ae00abde5e06d31651b0fe033d4ccab3d1bf4ec
parent7de0fd178d7b2dbccbf34cbffda38a1f4bdb4583 (diff)
.
-rw-r--r--2004/n/fpga/src/registre/registre.vhd3
1 files changed, 2 insertions, 1 deletions
diff --git a/2004/n/fpga/src/registre/registre.vhd b/2004/n/fpga/src/registre/registre.vhd
index 94be6c2..e0445fb 100644
--- a/2004/n/fpga/src/registre/registre.vhd
+++ b/2004/n/fpga/src/registre/registre.vhd
@@ -45,7 +45,7 @@ end entity;
architecture rtl of regIO is
-signal REG : T_DATA :=(others => '1');
+signal REG : T_DATA :=(others => '0');
begin
p_w:process(ck,load,input,rst)
@@ -104,3 +104,4 @@ end rtl;
+