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authorprot2004-02-12 11:07:56 +0000
committerprot2004-02-12 11:07:56 +0000
commit920018a9a8650623da4161d2f37c7ffacdf162a2 (patch)
tree2bf9e1fd85b2cdcb3f32202021106960e3ae01ac /2004
parentfbc352c9b3161d0f888321e52aeeaf2a682764d6 (diff)
Decodeur fitrant l'edresse.
Diffstat (limited to '2004')
-rw-r--r--2004/n/fpga/src/decodisa/decodisa.vhd36
1 files changed, 36 insertions, 0 deletions
diff --git a/2004/n/fpga/src/decodisa/decodisa.vhd b/2004/n/fpga/src/decodisa/decodisa.vhd
new file mode 100644
index 0000000..e75005f
--- /dev/null
+++ b/2004/n/fpga/src/decodisa/decodisa.vhd
@@ -0,0 +1,36 @@
+-- Décodeur de bus ISA pour le fpga robot
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+entity decodisa is
+generic(
+ myISA_adress: integer :=1234;
+ adr_bus_bit: integer :=10
+ );
+port(
+ ISA_clk: in std_logic;
+ ISA_RW: in std_logic; -- 1=read 0=write
+ ISA_adr_bus: in std_logic_vector(20 downto 0);
+
+ clk: out std_logic;
+ RW: out std_logic;
+ adr_bus: out std_logic_vector(20 downto 0);
+ );
+end entity;
+
+
+--
+architecture rtl of decodisa is
+signal myAdr: std_logic_vector(10 downto 0) := conv_std_logic_vector(integer(myISA_adress));
+
+begin
+process(ISA_adr_bus)
+ if(ISA_adr_bus=myAdr) then
+ adr_bus<=ISA_adr_bus;
+ else
+ adr_bus<=(others <= '0');
+ end if;
+end process;
+