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authorprot2004-02-24 10:13:17 +0000
committerprot2004-02-24 10:13:17 +0000
commit5a52e1850a7b577c4bf5cae98f638b915322b8f7 (patch)
tree3e3ece2969611f30cc74a5cad9b61b8efde870bf /2004
parent6e76f25f84a7a7be37057ca09ccd99b83aa4ded8 (diff)
.
Diffstat (limited to '2004')
-rw-r--r--2004/n/fpga/src/portserie/registre.vhd105
-rw-r--r--2004/n/fpga/src/portserie/test_reg.vhd76
2 files changed, 0 insertions, 181 deletions
diff --git a/2004/n/fpga/src/portserie/registre.vhd b/2004/n/fpga/src/portserie/registre.vhd
deleted file mode 100644
index 23a0079..0000000
--- a/2004/n/fpga/src/portserie/registre.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
--- txserie.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre Prot
--- registre IO adressable sur bus ISA
-
--- MARCHE
-
--- -------------------------------------------
--- Registre générique à brancher sur un bus
--- -------------------------------------------
---
--- * on peut écrire ou lire dans le registre depuis le bus :
--- . Positionner l'adresse
--- . Mettre 'rw' à 1=>read 0=>write
--- . Front montant sur 'ck'
--- Remarque : on ne peut pas écrire via le bus si 'load' est activé
--- * on peut lire la valeur en permanence sur 'output'
--- * on peut écrire dans le registre en permanence grâce à 'load'. Cette
--- action est prioritaire sur l'écriture via le bus
--- . Mettre 'load' à 1
--- . Ecrire dans 'input' (actualisation immédiate)
--- . Mettre 'load' à 0 pour latcher
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
-entity regIO is
- generic(adr : unsigned);
- port(
- bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
- input: in unsigned(7 downto 0);
- output: out unsigned(7 downto 0);
- rw: in std_logic;
- load: in std_logic;
- ck: in std_logic;
- rst: in std_logic
- );
-end entity;
-
-
-architecture rtl of regIO is
-signal REG : unsigned((NB_BIT_DATA - 1) downto 0):=(others => '1');
-
-begin
- p_w:process(ck,load,input,rst)
- begin
- if(ck='1') then
- if(bus_address=adr) then
- if(rw='0') then
- if(load='0') then
- REG<=bus_data;
- end if;
- else -- RW=1 : la CM lit => on écrit sur le bus
- bus_data<=REG;
- end if;
- else
- bus_data<=(others => 'Z');
- end if;
- else
- bus_data<=(others => 'Z');
- end if;
-
--- chargement : prioritaire sur l'écriture via le bus
- if(load='1') then
- REG<=input;
- end if;
-
--- reset : prioritaire sur tout
- if(rst'event and rst='1') then
- REG<=(others => '0');
- bus_data<=(others => 'Z');
- end if;
-
- end process p_w;
-
--- p_load : process(load,input)
--- begin
--- if(load='1') then
--- REG<=input;
--- end if;
--- end process p_load;
-
--- p_reset : process(rst)
--- begin
--- if(rst'event and rst='1') then
--- REG<=(others => '0');
--- bus_data<=(others => 'Z');
--- end if;
--- end process p_reset;
-
- output<=REG;
-end rtl;
-
-
-
-
-
-
-
diff --git a/2004/n/fpga/src/portserie/test_reg.vhd b/2004/n/fpga/src/portserie/test_reg.vhd
deleted file mode 100644
index 7573ba4..0000000
--- a/2004/n/fpga/src/portserie/test_reg.vhd
+++ /dev/null
@@ -1,76 +0,0 @@
--- testbench pour le registre
-
--- MARCHE
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
-entity testreg is
-constant adr_w : integer :=10;
-constant data_w : integer :=8;
-end testreg;
-
-architecture sim1 of testreg is
-component regIO
- generic(adr:unsigned);
- port(
- bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
- input: in unsigned((data_w - 1) downto 0);
- output: out unsigned((data_w - 1) downto 0);
- rw: in std_logic;
- load: in std_logic;
- ck: in std_logic;
- rst: in std_logic
- );
-end component;
-
-signal bus_address: unsigned((adr_w - 1) downto 0):="0000000000";
-signal bus_data: unsigned((data_w - 1) downto 0):="00000000";
-signal input: unsigned((data_w - 1) downto 0):="00000000";
-signal output: unsigned((data_w - 1) downto 0);
-signal rw: std_logic:='0';
-signal load: std_logic:='0';
-signal ck: std_logic:='0';
-signal rst: std_logic:='1';
-
-begin
- R0: regIO
- generic map(adr => "0000000001")
- port map(
- bus_address=>bus_address,
- bus_data=>bus_data,
- input=>input,
- output=>output,
- rw=>rw,
- load=>load,
- ck=>ck,
- rst=>rst
- );
-
- bus_address <= "0001001100" ,
- "0000000001" after 40 ns;
--- "0000001101" after 100 ns;
--- "0000001100" after 100 ns;
-
- input <= input + 1 after 3 ns;
- bus_data <= "01010101", "ZZZZZZZZ" after 2 ns;
- rw <= not rw after 11 ns;
- load <= not load after 7 ns;
- ck <= not ck after 5 ns;
- rst <= '0','1' after 1 ns,'0' after 2 ns;
-
-end sim1;
-
-
-configuration cf1 of testreg is
- for sim1
- for all : regIO use entity work.regIO(rtl); end for;
- end for;
-end cf1;
-
-