summaryrefslogtreecommitdiff
path: root/2004/n
diff options
context:
space:
mode:
authorgalmes2004-02-23 17:37:08 +0000
committergalmes2004-02-23 17:37:08 +0000
commit1507c7ba8fd6e8bf7f287e0d6f8355841b12c888 (patch)
tree4d1a2ea986180b1f97750d55522912dfa6a7030a /2004/n
parent4ccfe616f851d0ea39d6fe5ac0d18a37e66af74b (diff)
Ajout d'un nouveau type de registre.
Diffstat (limited to '2004/n')
-rw-r--r--2004/n/fpga/src/gpio/bch_reg_io.vhd27
-rw-r--r--2004/n/fpga/src/gpio/bch_reg_ioz.vhd67
-rw-r--r--2004/n/fpga/src/gpio/reg_io.vhd35
-rw-r--r--2004/n/fpga/src/gpio/reg_ioz.vhd54
-rw-r--r--2004/n/fpga/src/gpio/reg_rw.vhd10
5 files changed, 158 insertions, 35 deletions
diff --git a/2004/n/fpga/src/gpio/bch_reg_io.vhd b/2004/n/fpga/src/gpio/bch_reg_io.vhd
index f9fd5c9..a404427 100644
--- a/2004/n/fpga/src/gpio/bch_reg_io.vhd
+++ b/2004/n/fpga/src/gpio/bch_reg_io.vhd
@@ -1,7 +1,7 @@
-- bch_reg_io.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-André Galmes
--- Test de reg_rw.
+-- Test de reg_io.
library ieee;
use ieee.std_logic_1164.all;
@@ -22,8 +22,9 @@ architecture sim1 of bch_reg_io is
rst : in std_logic;
rw : in std_logic;
enable : in std_logic;
- data_in : inout T_DATA;
- data_out : inout T_DATA
+ data_f_in : inout T_DATA; -- forward in = entrée dans le sens direct.
+ data_out : out T_DATA;
+ data_b_in : in T_DATA -- backward in = entrée pour la lecture
);
end component;
@@ -31,16 +32,18 @@ architecture sim1 of bch_reg_io is
signal rst : std_logic;
signal rw : std_logic; -- read / write
signal enable : std_logic;
- signal data_in : T_DATA;
+ signal data_f_in : T_DATA;
signal data_out : T_DATA;
+ signal data_b_in : T_DATA;
begin
U1 : reg_io port map (
rst => rst,
rw => rw,
enable => enable,
- data_in => data_in,
- data_out => data_out
+ data_f_in => data_f_in,
+ data_out => data_out,
+ data_b_in => data_b_in
);
rst <= '1', '0' after CK_PERIOD;
@@ -50,13 +53,11 @@ begin
'1' after 5*CK_PERIOD,
'0' after 6*CK_PERIOD;
rw <= '1', '0' after 3*CK_PERIOD;
- data_in <= x"01",
- x"02" after 3*CK_PERIOD,
- "ZZZZZZZZ" after 5*CK_PERIOD;
- --x"03" after 5*CK_PERIOD;
- data_out <= "ZZZZZZZZ",
- x"07" after 5*CK_PERIOD,
- "ZZZZZZZZ" after 6*CK_PERIOD;
+ data_f_in <= x"01",
+ x"02" after 3*CK_PERIOD,
+ "ZZZZZZZZ" after 5*CK_PERIOD;
+ --x"03" after 5*CK_PERIOD;
+ data_b_in <= x"07";
end sim1;
configuration cf1_bch_reg_io of bch_reg_io is
diff --git a/2004/n/fpga/src/gpio/bch_reg_ioz.vhd b/2004/n/fpga/src/gpio/bch_reg_ioz.vhd
new file mode 100644
index 0000000..280bb63
--- /dev/null
+++ b/2004/n/fpga/src/gpio/bch_reg_ioz.vhd
@@ -0,0 +1,67 @@
+-- bch_reg_ioz.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Test de reg_rw.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.isa_const.all;
+use work.nono_const.all;
+
+
+entity bch_reg_ioz is
+end bch_reg_ioz;
+
+architecture sim1 of bch_reg_ioz is
+
+ component reg_ioz
+ port (
+ rst : in std_logic;
+ rw : in std_logic;
+ enable : in std_logic;
+ data_in : inout T_DATA;
+ data_out : inout T_DATA
+ );
+ end component;
+
+ -- définiton des signaux
+ signal rst : std_logic;
+ signal rw : std_logic; -- read / write
+ signal enable : std_logic;
+ signal data_in : T_DATA;
+ signal data_out : T_DATA;
+
+begin
+ U1 : reg_ioz port map (
+ rst => rst,
+ rw => rw,
+ enable => enable,
+ data_in => data_in,
+ data_out => data_out
+ );
+
+ rst <= '1', '0' after CK_PERIOD;
+ enable <= '0',
+ '1' after 2*CK_PERIOD,
+ '0' after 3*CK_PERIOD,
+ '1' after 5*CK_PERIOD,
+ '0' after 6*CK_PERIOD;
+ rw <= '1', '0' after 3*CK_PERIOD;
+ data_in <= x"01",
+ x"02" after 3*CK_PERIOD,
+ "ZZZZZZZZ" after 5*CK_PERIOD;
+ --x"03" after 5*CK_PERIOD;
+ data_out <= "ZZZZZZZZ",
+ x"07" after 5*CK_PERIOD,
+ "ZZZZZZZZ" after 6*CK_PERIOD;
+end sim1;
+
+configuration cf1_bch_reg_ioz of bch_reg_ioz is
+ for sim1
+ for all : reg_ioz use entity work.reg_ioz(BEHAV); end for;
+ end for;
+end cf1_bch_reg_ioz;
+
diff --git a/2004/n/fpga/src/gpio/reg_io.vhd b/2004/n/fpga/src/gpio/reg_io.vhd
index 951c56d..43416e4 100644
--- a/2004/n/fpga/src/gpio/reg_io.vhd
+++ b/2004/n/fpga/src/gpio/reg_io.vhd
@@ -1,15 +1,20 @@
-- reg_io.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-André Galmes
--- Registre dont on peut lire les valeurs sur data_out.
---
+-- Registre dont on peut lire les valeurs sur data_out.
+-- RQ : Ce type de registre a un inconvénient : la haute impédance !
+
+-- TODO : Principe :
+-- Si (write et enable) alors sauvegarde l'entrée data_f_in et copie
+-- entrée data_f_in sur sortie.
+-- Si (read et enable) alors copie entrée data_b_in sur entrée data_f_in.
+-- Si (pas enable) alors copie dernière valeur sauvegardée sur sortie.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-
use work.isa_const.all;
use work.nono_const.all;
@@ -17,13 +22,11 @@ use work.nono_const.all;
entity reg_io is
port (
rst : in std_logic;
-
- -- XXX : savoir si read = 0 ou 1 !!
- rw : in std_logic; -- read (0) / write (1)
+ rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
enable : in std_logic;
- data_in : inout T_DATA;
- data_out : inout T_DATA
- --data_direction : in T_DATA
+ data_f_in : inout T_DATA; -- forward in = entrée dans le sens direct.
+ data_out : out T_DATA;
+ data_b_in : in T_DATA -- backward in = entrée pour la lecture
);
end entity;
@@ -32,26 +35,22 @@ architecture BEHAV of reg_io is
signal REG : T_DATA;
begin
-- process
- process (rst, rw, enable, data_in)
+ process (rst, rw, enable, data_f_in, data_b_in)
begin
if (rst = '1') then
REG <= x"00";
- -- data_in <= "ZZZZZZZZ";
else
if (enable = '1') then
if (rw = ISA_WRITE) then
- REG <= data_in;
- -- data_out <= REG;
+ REG <= data_f_in;
elsif (rw = ISA_READ) then
- data_in <= data_out;
- -- data_in <= REG;
+ data_f_in <= data_b_in;
end if;
else
- data_in <= "ZZZZZZZZ";
- -- data_out <= REG;
+ data_f_in <= "ZZZZZZZZ";
end if;
end if;
end process;
- data_out <= "ZZZZZZZZ" when (rw = ISA_READ and enable = '1') else REG;
+ data_out <= REG;
end BEHAV;
diff --git a/2004/n/fpga/src/gpio/reg_ioz.vhd b/2004/n/fpga/src/gpio/reg_ioz.vhd
new file mode 100644
index 0000000..22f1730
--- /dev/null
+++ b/2004/n/fpga/src/gpio/reg_ioz.vhd
@@ -0,0 +1,54 @@
+-- reg_ioz.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Registre dont on peut lire les valeurs sur data_out.
+-- RQ : Ce type de registre a un inconvénient : la haute impédance !
+
+-- Principe :
+-- Si (write et enable) alors sauvegarde entrée et copie entrée sur sortie.
+-- Si (read et enable) alors copie sortie sur entrée.
+-- Si (pas enable) alors copie dernière valeur sauvegardée sur sortie.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.isa_const.all;
+use work.nono_const.all;
+
+
+entity reg_ioz is
+ port (
+ rst : in std_logic;
+ rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
+ enable : in std_logic;
+ data_in : inout T_DATA;
+ data_out : inout T_DATA
+ );
+end entity;
+
+architecture BEHAV of reg_ioz is
+ -- signal interne
+ signal REG : T_DATA;
+begin
+ -- process
+ process (rst, rw, enable, data_in)
+ begin
+ if (rst = '1') then
+ REG <= x"00";
+ else
+ if (enable = '1') then
+ if (rw = ISA_WRITE) then
+ REG <= data_in;
+ elsif (rw = ISA_READ) then
+ data_in <= data_out;
+ end if;
+ else
+ data_in <= "ZZZZZZZZ";
+ end if;
+ end if;
+ end process;
+
+ data_out <= "ZZZZZZZZ" when (rw = ISA_READ and enable = '1') else REG;
+end BEHAV;
diff --git a/2004/n/fpga/src/gpio/reg_rw.vhd b/2004/n/fpga/src/gpio/reg_rw.vhd
index 7350e76..b93121f 100644
--- a/2004/n/fpga/src/gpio/reg_rw.vhd
+++ b/2004/n/fpga/src/gpio/reg_rw.vhd
@@ -3,12 +3,16 @@
-- Auteur : Pierre-André Galmes
-- Registre dont la valeur est accessible en lecture.
+-- Principe :
+-- Si (write et enable) alors sauvegarde entrée et copie entrée sur sortie.
+-- Si (read et enable) alors copie dernière valeur sauvegardée sur entrée.
+-- Si (pas enable) alors copie dernière valeur sauvegardée sur sortie.
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-
use work.isa_const.all;
use work.nono_const.all;
@@ -16,9 +20,7 @@ use work.nono_const.all;
entity reg_rw is
port (
rst : in std_logic;
-
- -- XXX : savoir si read = 0 ou 1 !!
- rw : in std_logic; -- read (0) / write (1)
+ rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
enable : in std_logic;
data_in : inout T_DATA;
data_out : out T_DATA