summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/portserie/uart
diff options
context:
space:
mode:
authorprot2004-04-03 18:18:36 +0000
committerprot2004-04-03 18:18:36 +0000
commit2a8c2d3c2521de1599f6dc0d5a6b116d9c28bea3 (patch)
treea01bb0350004cc8f0b11cc61b31bde2680051be3 /2004/n/fpga/src/portserie/uart
parent9af180b06c093eda9f73bc7e15626cf5ae7ef623 (diff)
Modif aprs cration du top fpga.vhd
Diffstat (limited to '2004/n/fpga/src/portserie/uart')
-rw-r--r--2004/n/fpga/src/portserie/uart/txmit.vhd14
1 files changed, 8 insertions, 6 deletions
diff --git a/2004/n/fpga/src/portserie/uart/txmit.vhd b/2004/n/fpga/src/portserie/uart/txmit.vhd
index 0088729..76bfbf8 100644
--- a/2004/n/fpga/src/portserie/uart/txmit.vhd
+++ b/2004/n/fpga/src/portserie/uart/txmit.vhd
@@ -7,10 +7,10 @@ entity TXMIT is
MCLKX16 : in std_logic;
WRITE : in std_logic;
RESET : in std_logic;
- DATA : in std_logic_vector(7 downto 0);
+ DATA : in std_logic_vector(7 downto 0);
- TX : out std_logic;
- TXRDY : out std_logic
+ TX : out std_logic;
+ TXRDY : out std_logic
);
end TXMIT;
@@ -45,10 +45,12 @@ begin
TXDONE <= not (TAG2 or TAG1 or TSR(7) or TSR(6) or TSR(5) or TSR(4) or TSR(3)
or TSR(2) or TSR(1) or TSR(0));
+
+-- *** AJOUT ***
+ -- Ready for new date to be written, when no data is in transmit hold register.
+-- (ajout :) et quand la transmission est finie !
- -- Ready for new date to be written, when no data is in transmit hold register.
-
- TXRDY <= not TXDATARDY;
+ TXRDY <= TXDONE and not TXDATARDY;
-- Latch data[7:0] into the transmit hold register at posedge of write.