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authorprot2004-04-03 18:18:36 +0000
committerprot2004-04-03 18:18:36 +0000
commit2a8c2d3c2521de1599f6dc0d5a6b116d9c28bea3 (patch)
treea01bb0350004cc8f0b11cc61b31bde2680051be3 /2004/n/fpga/src/portserie/portserie/sfifo.xco
parent9af180b06c093eda9f73bc7e15626cf5ae7ef623 (diff)
Modif aprs cration du top fpga.vhd
Diffstat (limited to '2004/n/fpga/src/portserie/portserie/sfifo.xco')
-rw-r--r--2004/n/fpga/src/portserie/portserie/sfifo.xco5
1 files changed, 3 insertions, 2 deletions
diff --git a/2004/n/fpga/src/portserie/portserie/sfifo.xco b/2004/n/fpga/src/portserie/portserie/sfifo.xco
index a2badbd..cc7276e 100644
--- a/2004/n/fpga/src/portserie/portserie/sfifo.xco
+++ b/2004/n/fpga/src/portserie/portserie/sfifo.xco
@@ -18,11 +18,12 @@
# Number of HU_SETs used: 0
#
SET BusFormat = BusFormatAngleBracketNotRipped
+SET SimulationOutputProducts = VHDL
SET XilinxFamily = Spartan2
-SET OutputOption = OutputProducts
+SET OutputOption = DesignFlow
+SET DesignFlow = VHDL
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
-SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET data_width = 8
CSET read_error_sense = Active_Low