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authorprot2004-04-03 18:18:36 +0000
committerprot2004-04-03 18:18:36 +0000
commit2a8c2d3c2521de1599f6dc0d5a6b116d9c28bea3 (patch)
treea01bb0350004cc8f0b11cc61b31bde2680051be3 /2004/n/fpga/src/portserie/fifo
parent9af180b06c093eda9f73bc7e15626cf5ae7ef623 (diff)
Modif aprs cration du top fpga.vhd
Diffstat (limited to '2004/n/fpga/src/portserie/fifo')
-rw-r--r--2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd12
-rw-r--r--2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd6
-rw-r--r--2004/n/fpga/src/portserie/fifo/fifo.npl9
-rw-r--r--2004/n/fpga/src/portserie/fifo/fifodriver.vhd2
-rw-r--r--2004/n/fpga/src/portserie/fifo/sfifo.xco20
5 files changed, 25 insertions, 24 deletions
diff --git a/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
index a109693..94fa9a2 100644
--- a/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
+++ b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
@@ -41,7 +41,7 @@ signal data_count: std_logic_VECTOR(1 downto 0);
BEGIN
-Inst_fifodriver: fifodriver PORT MAP(
+uut: fifodriver PORT MAP(
clk => clk,
rst => rst,
readreq => readreq,
@@ -55,11 +55,11 @@ Inst_fifodriver: fifodriver PORT MAP(
);
- din <= std_logic_vector(unsigned(din) + 1) after 8 ns;
- rst<='1' , '0' after 10 ns;
- clk <= not clk after 1 ns;
- writereq <= not writereq after 13 ns;
- readreq <= not readreq after 17 ns;
+ din <= std_logic_vector(unsigned(din) + 1) after 400 ns;
+ rst<='1' , '0' after 510 ns;
+ clk <= not clk after 25 ns;
+ writereq <= not writereq after 700 ns;
+ readreq <= not readreq after 900 ns;
diff --git a/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd b/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd
index a3d930d..68b409f 100644
--- a/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd
+++ b/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd
@@ -44,7 +44,7 @@ signal wr_err: std_logic;
-- Component Instantiation
-U0 : sfifo
+uut : sfifo
port map (
clk => clk,
sinit => sinit,
@@ -60,11 +60,9 @@ U0 : sfifo
wr_err => wr_err,
data_count => data_count);
-
-
din <= std_logic_vector(unsigned(din) + 1) after 8 ns;
sinit <= '1' , '0' after 10 ns;
clk <= not clk after 3 ns;
rd_en <= '0' , '1' after 50 ns;
- END;
+ END behavior;
diff --git a/2004/n/fpga/src/portserie/fifo/fifo.npl b/2004/n/fpga/src/portserie/fifo/fifo.npl
index c8ba229..81fdd87 100644
--- a/2004/n/fpga/src/portserie/fifo/fifo.npl
+++ b/2004/n/fpga/src/portserie/fifo/fifo.npl
@@ -20,13 +20,16 @@ DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
STIMULUS bch_afifo.vhd
SOURCE fifodriver.vhd
-STIMULUS bch_fifodriver.vhd
SOURCE ..\..\modele\nono_const.vhd
-SOURCE sfifo.xco
STIMULUS bch_sfifo.vhd
+SOURCE sfifo.xco
+STIMULUS bch_fifodriver.vhd
[Normal]
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078952453, ModelSim SE
[STATUS-ALL]
-bch_fifodriver.vhd.testbenchRpt=ERRORS,0
+fifodriver.ngcFile=WARNINGS,1079734309
+fifodriver.ngdFile=WARNINGS,1079734329
+fifodriver.postMapVHDLSimModel=WARNINGS,1079734429
+sfifo.ngcFile=ERRORS,0
[STRATEGY-LIST]
Normal=True
diff --git a/2004/n/fpga/src/portserie/fifo/fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/fifodriver.vhd
index 3830e93..11d1955 100644
--- a/2004/n/fpga/src/portserie/fifo/fifodriver.vhd
+++ b/2004/n/fpga/src/portserie/fifo/fifodriver.vhd
@@ -61,7 +61,7 @@ signal wr_err:std_logic;
begin
-- Component Instantiation
-U0 : sfifo
+fifo0 : sfifo
port map (
clk => clk,
sinit => rst,
diff --git a/2004/n/fpga/src/portserie/fifo/sfifo.xco b/2004/n/fpga/src/portserie/fifo/sfifo.xco
index 306f531..236a635 100644
--- a/2004/n/fpga/src/portserie/fifo/sfifo.xco
+++ b/2004/n/fpga/src/portserie/fifo/sfifo.xco
@@ -5,13 +5,13 @@
# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\fifo
# OverwriteFiles = true
# Core name: sfifo
-# Number of Primitives in design: 120
+# Number of Primitives in design: 87
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
-# Number of LUT sites used in design: 70
-# Number of LUTs used in design: 46
-# Number of REG used in design: 24
-# Number of SRL16s used in design: 24
+# Number of LUT sites used in design: 43
+# Number of LUTs used in design: 35
+# Number of REG used in design: 22
+# Number of SRL16s used in design: 8
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
@@ -25,18 +25,18 @@ SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET data_width = 8
-CSET read_error_sense = active_high
+CSET read_error_sense = Active_Low
CSET read_error_flag = true
CSET write_acknowledge_flag = true
CSET write_error_flag = true
CSET data_count = true
CSET memory_type = Distributed_Memory
-CSET read_acknowledge_sense = active_high
+CSET read_acknowledge_sense = Active_Low
CSET component_name = sfifo
-CSET fifo_depth = 32
+CSET fifo_depth = 16
CSET read_acknowledge_flag = true
CSET data_count_width = 2
-CSET write_error_sense = active_high
-CSET write_acknowledge_sense = active_high
+CSET write_error_sense = Active_Low
+CSET write_acknowledge_sense = Active_Low
GENERATE