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authorprot2004-03-01 16:16:05 +0000
committerprot2004-03-01 16:16:05 +0000
commit16cbbd83d43093a12fbb18f0287fda5c286c28a7 (patch)
tree9fbd722678826f7502f099d0cc9dcffc9e0cfca6 /2004/n/fpga/src/portserie/fifo.vhd
parent76098ead389c3803b9d5b47c8f6e915e1123b03a (diff)
Modif du txserie pour adaptiation a la fifo coregen
// // // // a l'UART efrei
Diffstat (limited to '2004/n/fpga/src/portserie/fifo.vhd')
-rw-r--r--2004/n/fpga/src/portserie/fifo.vhd8
1 files changed, 4 insertions, 4 deletions
diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd
index 9023596..7122c96 100644
--- a/2004/n/fpga/src/portserie/fifo.vhd
+++ b/2004/n/fpga/src/portserie/fifo.vhd
@@ -34,8 +34,8 @@ component fifodriver is
);
end component;
---component fifoctlr_cc is
-component fifobehav is
+component fifoctlr_cc is
+--component fifobehav is
port (clock_in: IN std_logic;
read_enable_in: IN std_logic;
write_enable_in: IN std_logic;
@@ -70,8 +70,8 @@ begin
---FIFO1:fifoctlr_cc
-FIFO1:fifobehav
+FIFO1:fifoctlr_cc
+--FIFO1:fifobehav
port map(
clock_in=>clock_fifo,
read_enable_in=>read_enable,