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authorprot2004-02-26 21:58:25 +0000
committerprot2004-02-26 21:58:25 +0000
commit872a5b43d413383e6a841910397417a084e9057f (patch)
tree2341484d70958e996fd76c067a0537ee59bcccfe /2004/n/fpga/src/portserie/bch_txserie.vhd
parentdcc10693309c53b204189aadf7163718fc1695f6 (diff)
On avance on avance...
Diffstat (limited to '2004/n/fpga/src/portserie/bch_txserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/bch_txserie.vhd72
1 files changed, 61 insertions, 11 deletions
diff --git a/2004/n/fpga/src/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/bch_txserie.vhd
index 735078d..d1aa1e3 100644
--- a/2004/n/fpga/src/portserie/bch_txserie.vhd
+++ b/2004/n/fpga/src/portserie/bch_txserie.vhd
@@ -40,20 +40,22 @@ architecture sim1 of bch_txserie is
-- définiton des signaux
signal rst : std_logic;
signal clk : std_logic := '0';
+signal simclk : std_logic := '0';
signal rw : std_logic; -- read / write
signal bus_data : T_DATA:="00000000";
signal bus_address : T_ADDRESS;
signal masterck: std_logic:='0';
signal txout: std_logic;
signal minIRQ: std_logic;
+signal state_next:integer:=0;
begin
U1 : txserie
generic map (
-- Définition des addresses.
- A_DATA => "0000000011",
- A_CONFIG => "0000000100",
- A_FLAG => "0000000010"
+ A_DATA => "0000000001",
+ A_CONFIG => "0000000010",
+ A_FLAG => "0000000011"
)
port map (
rst => rst,
@@ -66,15 +68,62 @@ begin
minIRQ=> minIRQ
);
- rst <= '1', '0' after CK_PERIOD;
- clk <= not clk after (CK_PERIOD);
- rw <= '0';
- bus_address <= "0000000011",
- "0000000100" after 6*CK_PERIOD,
- "0000000100" after 10*CK_PERIOD,
- "0000000011" after 16*CK_PERIOD;
- bus_data <= "01010101";--) after 10 ns;
+
masterck<= not masterck after (CK_PERIOD/11);
+ simclk<= not simclk after (CK_PERIOD/2);
+
+
+ process(simclk)
+ begin
+ if(simclk'event and simclk='1') then
+ state_next<=(state_next + 1);
+ end if;
+ end process;
+
+ process(state_next)
+ begin
+ bus_address<="0000000000";
+ clk<='0';
+ rst<='0';
+ bus_data<=(others =>'Z');
+
+ case state_next is
+ when 1 => bus_address<="0000000010";
+ bus_data<="00010111";
+ rw<='0';
+ when 2 => bus_address<="0000000010";
+ bus_data<="00010111";
+ rw<='0';
+ clk<='1';
+ when 3 => null;
+
+ when 4 => bus_address<="0000000001";
+ bus_data<="00010111";
+ rw<='0';
+ when 5 => bus_address<="0000000001";
+ bus_data<="00010111";
+ rw<='0';
+ clk<='1';
+ when 6 => null;
+
+ when 7 => bus_address<="0000000011";
+ rw<='1';
+ when 8 => bus_address<="0000000011";
+ rw<='1';
+ clk<='1';
+ when 9 => null;
+
+
+ when 10 => bus_address<="0000000010";
+ rw<='1';
+ when 11 => bus_address<="0000000010";
+ rw<='1';
+ clk<='1';
+ when 12 => null;
+
+ when others => null;
+ end case;
+ end process;
end sim1;
@@ -88,3 +137,4 @@ end cf1_bch_txserie;
+