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authorgalmes2004-03-30 15:10:52 +0000
committergalmes2004-03-30 15:10:52 +0000
commit8e39188d2a674e7cc3ab0639c62e3e680bbed8fe (patch)
tree2d341f7596fd2ead29be050fddbb3c34cdb066c6 /2004/n/fpga/src/or/or3.vhd
parent33a615e793066c19388fed03aef70cc5213e6479 (diff)
interrupt : Version Fonctionnelle testée sur carte (avec caméra intégrée).
Diffstat (limited to '2004/n/fpga/src/or/or3.vhd')
-rw-r--r--2004/n/fpga/src/or/or3.vhd17
1 files changed, 8 insertions, 9 deletions
diff --git a/2004/n/fpga/src/or/or3.vhd b/2004/n/fpga/src/or/or3.vhd
index 48ae2c8..b59a48e 100644
--- a/2004/n/fpga/src/or/or3.vhd
+++ b/2004/n/fpga/src/or/or3.vhd
@@ -12,18 +12,17 @@ use work.isa_const.all;
use work.nono_const.all;
-entity or3 is
+entity or3_nono is
port (
- in1 : in std_logic;
- in2 : in std_logic;
- in3 : in std_logic;
- or_out : out std_logic
+ or3_in1 : in std_logic;
+ or3_in2 : in std_logic;
+ or3_in3 : in std_logic;
+ or3_out : out std_logic
);
end entity;
-architecture RTL of or3 is
+architecture RTL of or3_nono is
begin
-
- or_out <= '1' when (in1 = '1' or
- in2 = '1' or in3 ='1') else '0';
+ or3_out <= '1' when (or3_in1 = '1' or
+ or3_in2 = '1' or or3_in3 ='1') else '0';
end RTL;