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authorgalmes2004-03-03 22:17:05 +0000
committergalmes2004-03-03 22:17:05 +0000
commitd20e1be6c4dc816cfb96a2fc5335144967139859 (patch)
tree025b01b387b19aa0ff8f2d0a0f2f015948bdcbdb /2004/n/fpga/src/interrupt
parent3f0458c3087881ee7e3a07f0838a692c93b0919f (diff)
Interrupt : début du bloc conserv :)
Diffstat (limited to '2004/n/fpga/src/interrupt')
-rw-r--r--2004/n/fpga/src/interrupt/conserv.vhd55
1 files changed, 42 insertions, 13 deletions
diff --git a/2004/n/fpga/src/interrupt/conserv.vhd b/2004/n/fpga/src/interrupt/conserv.vhd
index 97a13f7..285c363 100644
--- a/2004/n/fpga/src/interrupt/conserv.vhd
+++ b/2004/n/fpga/src/interrupt/conserv.vhd
@@ -24,26 +24,55 @@ entity conserv is
end entity;
architecture RTL of conserv is
+
+ -- Signal interne
+ -- registres à décalage pour compter 2 cycles.
+ signal reg_dec0 : std_logic_vector (2 downto 0);
+ signal reg_dec1 : std_logic_vector (2 downto 0);
+ signal reg_dec2 : std_logic_vector (2 downto 0);
+ signal reg_dec3 : std_logic_vector (2 downto 0);
+ signal reg_dec4 : std_logic_vector (2 downto 0);
+ signal reg_dec5 : std_logic_vector (2 downto 0);
+ signal reg_dec6 : std_logic_vector (2 downto 0);
+ signal reg_dec7 : std_logic_vector (2 downto 0);
+
begin
-- process séquentiel
process (rst, clk)
begin
if (rst = '1') then
- -- ne pas déclencher d'it après rst.
- data_out <= x"00";
+ data_out <= x"00";
+-- reg_dec0 <= "000";
+-- reg_dec1 <= "000";
+-- reg_dec2 <= "000";
+-- reg_dec3 <= "000";
+-- reg_dec4 <= "000";
+-- reg_dec5 <= "000";
+-- reg_dec6 <= "000";
+-- reg_dec7 <= "000";
elsif (clk'event and clk = '1') then
- if (data_in(0) = '1') then
- data_out(0) <= '1'; end if;
- if (data_in(1) = '1') then data_out(1) <= '1'; end if;
- if (data_in(2) = '1') then data_out(2) <= '1'; end if;
- if (data_in(3) = '1') then data_out(3) <= '1'; end if;
- if (data_in(4) = '1') then data_out(4) <= '1'; end if;
- if (data_in(5) = '1') then data_out(5) <= '1'; end if;
- if (data_in(6) = '1') then data_out(6) <= '1'; end if;
- if (data_in(7) = '1') then data_out(7) <= '1'; end if;
- -- Détection des interruptions.
- if (data_in /= x"00") then it_detected <= '1'; end if;
+ --
+ if (cycle = "SS") then -- TODO
+ cycle <= "00";
+ end if;
+ --
+ if (data_in /= x"00") then
+
+ state_p <= data_in;
+
+ if (cycle = "01") then
+ cycle <= cycle + 1; -- TODO : vérifier que valable.
+ if (data_out /= state_p) then
+ data_out <= state_p;
+ end if;
+ end if;
+ end if;
+
+
end if;
end process;
+ -- process combinatoire.
+ data_out <=
+
end RTL;