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authorgalmes2004-02-28 22:14:30 +0000
committergalmes2004-02-28 22:14:30 +0000
commit74113ba7738606383d83e44d8ab75d85d8fe1166 (patch)
tree4ab74b6a83a4f570301bf6bdd3eec5b916f2f420 /2004/n/fpga/src/interrupt
parent7ac4ade1a941c90d23891c5332f9f9b869107977 (diff)
Déplacement dans le rep registre
Diffstat (limited to '2004/n/fpga/src/interrupt')
-rw-r--r--2004/n/fpga/src/interrupt/bch_reg_8.vhd54
-rw-r--r--2004/n/fpga/src/interrupt/reg_8.vhd33
2 files changed, 0 insertions, 87 deletions
diff --git a/2004/n/fpga/src/interrupt/bch_reg_8.vhd b/2004/n/fpga/src/interrupt/bch_reg_8.vhd
deleted file mode 100644
index 4538de2..0000000
--- a/2004/n/fpga/src/interrupt/bch_reg_8.vhd
+++ /dev/null
@@ -1,54 +0,0 @@
--- bch_reg_8.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- test bench du registre 8 bits
-
-library ieee;
-use ieee.std_logic_1164.all;
---use ieee.std_logic_arith.all;
-
-use work.nono_const.all;
-
-entity bch_reg_8 is
-end bch_reg_8;
-
-architecture sim_1 of bch_reg_8 is
- component reg_8
- port(
- rst : in std_logic;
- clk : in std_logic;
- en : in std_logic; -- enable
- input : in std_logic_vector (7 downto 0);
- output : out std_logic_vector (7 downto 0)
- );
- end component;
- signal rst : std_logic;
- signal clk : std_logic := '0';
- signal en : std_logic := '0';
- signal input : std_logic_vector (7 downto 0);
- signal output : std_logic_vector (7 downto 0);
-
- begin
- U0 : reg_8 port map (rst => rst, clk => clk, en => en,
- input => input, output => output);
-
- rst <= '1', '0' after (CK_PERIOD/5);
- clk <= not clk after CK_PERIOD/2;
- en <= '0',
- '1' after (CK_PERIOD*1),
- '0' after (CK_PERIOD*3),
- '1' after (CK_PERIOD*5),
- '0' after (CK_PERIOD*7);
- input <= x"00",
- x"05" after (CK_PERIOD/2),
- x"01" after (CK_PERIOD*3);
-
-end sim_1;
-
---configuration
-
-configuration cf_bch_reg_8 of bch_reg_8 is
- for sim_1
- for U0 : reg_8 use entity work.reg_8(RTL); end for;
- end for;
-end cf_bch_reg_8;
diff --git a/2004/n/fpga/src/interrupt/reg_8.vhd b/2004/n/fpga/src/interrupt/reg_8.vhd
deleted file mode 100644
index f32f7d9..0000000
--- a/2004/n/fpga/src/interrupt/reg_8.vhd
+++ /dev/null
@@ -1,33 +0,0 @@
--- reg_8.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Registre 8 bits.
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-
-entity reg_8 is
- port (
- rst : in std_logic;
- clk : in std_logic;
- en : in std_logic; -- enable
- input : in std_logic_vector (7 downto 0);
- output : out std_logic_vector (7 downto 0)
- );
-end reg_8;
-
-architecture RTL of reg_8 is
-begin
- process (rst, clk)
- begin
- if (rst ='1') then
- output <= x"00";
- elsif (clk'event and clk = '1') then
- if (en='1') then
- output <= input;
- end if;
- end if;
- end process;
-end RTL;