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authorgalmes2004-03-31 12:28:51 +0000
committergalmes2004-03-31 12:28:51 +0000
commit69cb1ce8d0d17be955870d300ee50c61ce797c6d (patch)
tree5b158f3a17db1839c19c681ab0f164c8ad7871a8 /2004/n/fpga/src/gpio
parent8ee0be4e268b7591ed7c0ed871722df709ddf1c0 (diff)
Gpio2 : version des gpio avec détection sur front montant ET / OU descendant.
Diffstat (limited to '2004/n/fpga/src/gpio')
-rw-r--r--2004/n/fpga/src/gpio/gpio2.vhd193
1 files changed, 193 insertions, 0 deletions
diff --git a/2004/n/fpga/src/gpio/gpio2.vhd b/2004/n/fpga/src/gpio/gpio2.vhd
new file mode 100644
index 0000000..d8ba9b6
--- /dev/null
+++ b/2004/n/fpga/src/gpio/gpio2.vhd
@@ -0,0 +1,193 @@
+-- gpio.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- General Purpose Public Output.
+
+-- Caractéristiques :
+-- paramétrage de chaque pin en entrée ou sortie.
+-- paramétrage de la détection des interruptions (front montant et/ou
+-- descendant).
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+entity gpio is
+ port(
+ rst : in std_logic;
+ clk_b : in std_logic; -- clock de bus
+ clk_m : in std_logic; -- master clock
+ rw : in std_logic; -- read (0) / write (1) TODO ??
+ interrupt : out std_logic;
+ bus_data : inout T_DATA;
+ io_output : inout T_DATA;
+ -- chip select
+ cs_reg_data : in std_logic;
+ cs_reg_direction : in std_logic;
+ cs_reg_it_up_mask : in std_logic;
+ cs_reg_it_down_mask : in std_logic;
+ cs_read_output : in std_logic
+ );
+end entity;
+
+architecture RTL of gpio is
+
+-- Définition des composants utilisés.
+
+-- TODO : CONtinuer à partir d'ICICICICCICIC
+
+-- Registre.
+component reg_rw is
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
+ enable : in std_logic;
+ data : inout T_DATA;
+ data_out : out T_DATA -- data courant
+ );
+end component;
+
+-- ET bit à bit à sortie three state.
+component gpio_direction is
+ port (
+ direction_mask : in T_DATA;
+ data_in : in T_DATA;
+ data_out : out T_DATA
+ );
+end component;
+
+-- détecteur de changement d'état sur front descendant 8 bits.
+component gpio_it_detect_down is
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ data_in : in T_DATA;
+ it_mask : in T_DATA;
+ it_detected : out std_logic
+ );
+end component;
+
+-- détecteur de changement d'état sur front montant 8 bits.
+component gpio_it_detect_up is
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ data_in : in T_DATA;
+ it_mask : in T_DATA;
+ it_detected : out std_logic
+ );
+end component;
+
+-- Composant three-state.
+component tristate is
+ port (
+ rst : std_logic;
+ clk : std_logic;
+ enable : in std_logic;
+ data_in : in T_DATA;
+ data_out : out T_DATA
+ );
+end component;
+
+-- définition des signaux.
+-- clk, rst... sont définis dans l'entity du GPIO.
+--
+signal bus_direction_mask : T_DATA;
+signal bus_it_up_mask : T_DATA;
+signal bus_it_down_mask : T_DATA;
+signal bus_reg_data : T_DATA;
+signal rst_it : std_logic;
+
+begin
+
+-- Mapping des composants.
+
+--
+Reg_direction_mask : reg_rw
+port map (
+ clk_b,
+ rst,
+ rw,
+ cs_reg_direction,
+ bus_data,
+ bus_direction_mask
+);
+
+--
+Reg_data : reg_rw
+port map (
+ clk_b,
+ rst,
+ rw,
+ cs_reg_data,
+ bus_data,
+ bus_reg_data
+);
+
+--
+Reg_it_up_mask : reg_rw
+port map (
+ clk_b,
+ rst,
+ rw,
+ cs_reg_it_up_mask,
+ bus_data,
+ bus_it_up_mask
+);
+
+--
+Reg_it_down_mask : reg_rw
+port map (
+ clk_b,
+ rst,
+ rw,
+ cs_reg_it_down_mask,
+ bus_data,
+ bus_it_down_mask
+);
+
+--
+read_output : tristate
+port map (
+ rst,
+ clk_b,
+ cs_read_output,
+ io_output,
+ bus_data
+);
+
+--
+gest_direction : gpio_direction
+port map (
+ bus_direction_mask,
+ bus_reg_data,
+ io_output
+);
+
+-- signal intermédiaire.
+rst_it <= rst or cs_read_output;
+
+--
+it_up_detector : gpio_it_detect
+port map (
+ clk_m,
+ rst_it,
+ io_output,
+ bus_it_up_mask,
+ interrupt
+);
+
+it_down_detector : gpio_it_detect
+port map (
+ clk_m,
+ rst_it,
+ io_output,
+ bus_it_down_mask,
+ interrupt
+);
+
+end RTL;