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authorgalmes2004-02-23 13:56:11 +0000
committergalmes2004-02-23 13:56:11 +0000
commit35a62b404da36bf239aa8954c286efa6c2bb925d (patch)
tree39a4b6efe5f59ff44ad81b697b3bab88f39e5d26 /2004/n/fpga/src/gpio
parentabc842ae6d7f4907629dfd53f53d84c1122eb52a (diff)
Ajout du code fait pendant les vacances + modifications sur le modèle
Diffstat (limited to '2004/n/fpga/src/gpio')
-rw-r--r--2004/n/fpga/src/gpio/bch_reg_io.vhd67
-rw-r--r--2004/n/fpga/src/gpio/bch_reg_rw.vhd64
-rw-r--r--2004/n/fpga/src/gpio/reg_io.vhd57
-rw-r--r--2004/n/fpga/src/gpio/reg_rw.vhd52
4 files changed, 240 insertions, 0 deletions
diff --git a/2004/n/fpga/src/gpio/bch_reg_io.vhd b/2004/n/fpga/src/gpio/bch_reg_io.vhd
new file mode 100644
index 0000000..f9fd5c9
--- /dev/null
+++ b/2004/n/fpga/src/gpio/bch_reg_io.vhd
@@ -0,0 +1,67 @@
+-- bch_reg_io.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Test de reg_rw.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.isa_const.all;
+use work.nono_const.all;
+
+
+entity bch_reg_io is
+end bch_reg_io;
+
+architecture sim1 of bch_reg_io is
+
+ component reg_io
+ port (
+ rst : in std_logic;
+ rw : in std_logic;
+ enable : in std_logic;
+ data_in : inout T_DATA;
+ data_out : inout T_DATA
+ );
+ end component;
+
+ -- définiton des signaux
+ signal rst : std_logic;
+ signal rw : std_logic; -- read / write
+ signal enable : std_logic;
+ signal data_in : T_DATA;
+ signal data_out : T_DATA;
+
+begin
+ U1 : reg_io port map (
+ rst => rst,
+ rw => rw,
+ enable => enable,
+ data_in => data_in,
+ data_out => data_out
+ );
+
+ rst <= '1', '0' after CK_PERIOD;
+ enable <= '0',
+ '1' after 2*CK_PERIOD,
+ '0' after 3*CK_PERIOD,
+ '1' after 5*CK_PERIOD,
+ '0' after 6*CK_PERIOD;
+ rw <= '1', '0' after 3*CK_PERIOD;
+ data_in <= x"01",
+ x"02" after 3*CK_PERIOD,
+ "ZZZZZZZZ" after 5*CK_PERIOD;
+ --x"03" after 5*CK_PERIOD;
+ data_out <= "ZZZZZZZZ",
+ x"07" after 5*CK_PERIOD,
+ "ZZZZZZZZ" after 6*CK_PERIOD;
+end sim1;
+
+configuration cf1_bch_reg_io of bch_reg_io is
+ for sim1
+ for all : reg_io use entity work.reg_io(BEHAV); end for;
+ end for;
+end cf1_bch_reg_io;
+
diff --git a/2004/n/fpga/src/gpio/bch_reg_rw.vhd b/2004/n/fpga/src/gpio/bch_reg_rw.vhd
new file mode 100644
index 0000000..7d4a41a
--- /dev/null
+++ b/2004/n/fpga/src/gpio/bch_reg_rw.vhd
@@ -0,0 +1,64 @@
+-- bch_reg_rw.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Test de reg_rw.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.isa_const.all;
+use work.nono_const.all;
+
+
+entity bch_reg_rw is
+end bch_reg_rw;
+
+architecture sim1 of bch_reg_rw is
+
+ component reg_rw
+ port (
+ rst : in std_logic;
+ rw : in std_logic;
+ enable : in std_logic;
+ data_in : inout T_DATA;
+ data_out : out T_DATA
+ );
+ end component;
+
+ -- définiton des signaux
+ signal rst : std_logic;
+ signal rw : std_logic; -- read / write
+ signal enable : std_logic;
+ signal data_in : T_DATA;
+ signal data_out : T_DATA;
+
+begin
+ U1 : reg_rw port map (
+ rst => rst,
+ rw => rw,
+ enable => enable,
+ data_in => data_in,
+ data_out => data_out
+ );
+
+ rst <= '1', '0' after CK_PERIOD;
+ enable <= '0',
+ '1' after 2*CK_PERIOD,
+ '0' after 3*CK_PERIOD,
+ '1' after 5*CK_PERIOD,
+ '0' after 6*CK_PERIOD;
+ rw <= '1', '0' after 3*CK_PERIOD;
+ data_in <= x"01",
+ x"02" after 3*CK_PERIOD,
+ "ZZZZZZZZ" after 5*CK_PERIOD;
+ --x"03" after 5*CK_PERIOD;
+end sim1;
+
+configuration cf1_bch_reg_rw of bch_reg_rw is
+ for sim1
+ for all : reg_rw use entity work.reg_rw(BEHAV); end for;
+ end for;
+end cf1_bch_reg_rw;
+
diff --git a/2004/n/fpga/src/gpio/reg_io.vhd b/2004/n/fpga/src/gpio/reg_io.vhd
new file mode 100644
index 0000000..951c56d
--- /dev/null
+++ b/2004/n/fpga/src/gpio/reg_io.vhd
@@ -0,0 +1,57 @@
+-- reg_io.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Registre dont on peut lire les valeurs sur data_out.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+use work.isa_const.all;
+use work.nono_const.all;
+
+
+entity reg_io is
+ port (
+ rst : in std_logic;
+
+ -- XXX : savoir si read = 0 ou 1 !!
+ rw : in std_logic; -- read (0) / write (1)
+ enable : in std_logic;
+ data_in : inout T_DATA;
+ data_out : inout T_DATA
+ --data_direction : in T_DATA
+ );
+end entity;
+
+architecture BEHAV of reg_io is
+ -- signal interne
+ signal REG : T_DATA;
+begin
+ -- process
+ process (rst, rw, enable, data_in)
+ begin
+ if (rst = '1') then
+ REG <= x"00";
+ -- data_in <= "ZZZZZZZZ";
+ else
+ if (enable = '1') then
+ if (rw = ISA_WRITE) then
+ REG <= data_in;
+ -- data_out <= REG;
+ elsif (rw = ISA_READ) then
+ data_in <= data_out;
+ -- data_in <= REG;
+ end if;
+ else
+ data_in <= "ZZZZZZZZ";
+ -- data_out <= REG;
+ end if;
+ end if;
+ end process;
+
+ data_out <= "ZZZZZZZZ" when (rw = ISA_READ and enable = '1') else REG;
+end BEHAV;
diff --git a/2004/n/fpga/src/gpio/reg_rw.vhd b/2004/n/fpga/src/gpio/reg_rw.vhd
new file mode 100644
index 0000000..7350e76
--- /dev/null
+++ b/2004/n/fpga/src/gpio/reg_rw.vhd
@@ -0,0 +1,52 @@
+-- reg_rw.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Registre dont la valeur est accessible en lecture.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+use work.isa_const.all;
+use work.nono_const.all;
+
+
+entity reg_rw is
+ port (
+ rst : in std_logic;
+
+ -- XXX : savoir si read = 0 ou 1 !!
+ rw : in std_logic; -- read (0) / write (1)
+ enable : in std_logic;
+ data_in : inout T_DATA;
+ data_out : out T_DATA
+ );
+end entity;
+
+architecture BEHAV of reg_rw is
+ -- signal interne
+ signal REG : T_DATA;
+begin
+ -- process d'écriture.
+ process (rst, rw, enable, data_in)
+ begin
+ if (rst = '1') then
+ REG <= x"00";
+ else
+ if (enable = '1') then
+ if (rw = ISA_WRITE) then
+ REG <= data_in;
+ elsif (rw = ISA_READ) then
+ data_in <= REG;
+ end if;
+ else
+ data_in <= "ZZZZZZZZ";
+ end if;
+ end if;
+ end process;
+
+ --
+ data_out <= REG;
+end BEHAV;