summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/gpio/reg_rw.vhd
diff options
context:
space:
mode:
authorgalmes2004-02-24 21:30:40 +0000
committergalmes2004-02-24 21:30:40 +0000
commit3a46e687fadd28f93b3a67063e535615770a966d (patch)
tree34754ade1fc5c013c08c3701fbdcbca1382f44c4 /2004/n/fpga/src/gpio/reg_rw.vhd
parentf8ee5b24be92c6709781e17c6f8ff358f5986558 (diff)
Ajout de plein de fichier pour faire les gpio
Diffstat (limited to '2004/n/fpga/src/gpio/reg_rw.vhd')
-rw-r--r--2004/n/fpga/src/gpio/reg_rw.vhd35
1 files changed, 17 insertions, 18 deletions
diff --git a/2004/n/fpga/src/gpio/reg_rw.vhd b/2004/n/fpga/src/gpio/reg_rw.vhd
index b93121f..1c81139 100644
--- a/2004/n/fpga/src/gpio/reg_rw.vhd
+++ b/2004/n/fpga/src/gpio/reg_rw.vhd
@@ -19,36 +19,35 @@ use work.nono_const.all;
entity reg_rw is
port (
+ clk : in std_logic;
rst : in std_logic;
rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
enable : in std_logic;
- data_in : inout T_DATA;
- data_out : out T_DATA
+ data : inout T_DATA;
+ data_out : out T_DATA -- data courant
);
end entity;
-architecture BEHAV of reg_rw is
+architecture RTL of reg_rw is
-- signal interne
signal REG : T_DATA;
begin
- -- process d'écriture.
- process (rst, rw, enable, data_in)
+ -- partie séquentielle.
+ process (rst, clk)
begin
+ -- reset
if (rst = '1') then
- REG <= x"00";
- else
- if (enable = '1') then
- if (rw = ISA_WRITE) then
- REG <= data_in;
- elsif (rw = ISA_READ) then
- data_in <= REG;
- end if;
- else
- data_in <= "ZZZZZZZZ";
+ REG <= (others => '0');
+ -- écriture des données.
+ elsif (clk'event and clk = '1') then
+ if (enable = '1' and rw = ISA_WRITE) then
+ REG <= data;
end if;
end if;
end process;
-
- --
+
+ -- partie combinatoire.
+ data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z');
data_out <= REG;
-end BEHAV;
+
+end RTL;