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authorprot2004-04-03 18:18:36 +0000
committerprot2004-04-03 18:18:36 +0000
commit2a8c2d3c2521de1599f6dc0d5a6b116d9c28bea3 (patch)
treea01bb0350004cc8f0b11cc61b31bde2680051be3 /2004/n/fpga/src/fpga/fpga-test.vhd
parent9af180b06c093eda9f73bc7e15626cf5ae7ef623 (diff)
Modif aprs cration du top fpga.vhd
Diffstat (limited to '2004/n/fpga/src/fpga/fpga-test.vhd')
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+
+-- VHDL Test Bench Created from source file fpga.vhd -- 17:38:53 03/30/2004
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.std_logic_arith.all;
+USE ieee.numeric_std.ALL;
+
+use work.nono_const.all;
+use work.isa_const.all;
+
+ENTITY bch_fpga IS
+END bch_fpga;
+
+ARCHITECTURE behavior OF bch_fpga IS
+ COMPONENT fpga
+ PORT(
+ rst : IN std_logic;
+ clk_speed : IN std_logic;
+ clk_ref : IN std_logic;
+ AEN : IN std_logic;
+ IOR : IN std_logic;
+ IOW : IN std_logic;
+ bus_adr : IN std_logic_vector(23 downto 0);
+ rxin1 : IN std_logic;
+ bus_data : INOUT std_logic_vector(7 downto 0);
+ irq : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ SIGNAL rst : std_logic:='0';
+ SIGNAL clk_speed : std_logic:='0';
+ SIGNAL clk_ref : std_logic:='0';
+ SIGNAL AEN : std_logic;
+ SIGNAL IOR : std_logic;
+ SIGNAL IOW : std_logic;
+ SIGNAL bus_adr : std_logic_vector(23 downto 0);
+ SIGNAL bus_data : std_logic_vector(7 downto 0);
+ SIGNAL irq : std_logic;
+ SIGNAL rxin1 : std_logic:='0';
+
+ signal data : integer;
+ signal data_received : std_logic_vector(7 downto 0);
+
+BEGIN
+
+ uut: fpga PORT MAP(
+ rst => rst,
+ clk_speed => clk_speed,
+ clk_ref => clk_ref,
+ AEN => AEN,
+ IOR => IOR,
+ IOW => IOW,
+ bus_adr => bus_adr,
+ bus_data => bus_data,
+ irq => irq,
+ rxin1 => rxin1
+ );
+
+-- master clock
+clk_speed <= (Not clk_speed) after (CK_PERIOD/2);
+-- Reset
+rst <= '1','0' after (10*CK_PERIOD);
+
+-- baudrate/(16*2) used to generate half clock cycle;
+clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz
+-- feeding back output from transmitter to the input of receiver
+rxin1 <= (not rxin1) after 15751 ns;
+
+
+check:process
+ -- procedure declaration
+ -- declared in process due to assignment to read
+ -- this procedure reads out data from the receiver
+ -- timing can be modified to model any CPU read cycle
+ PROCEDURE read_bus(address : in integer) IS
+ variable adr : std_logic_vector(23 downto 0);
+ BEGIN
+ adr:=conv_std_logic_vector(address,24);
+ bus_data<="ZZZZZZZZ";
+ AEN<='0';
+ WAIT FOR 20 ns;
+ bus_adr<=adr;
+ WAIT FOR 20 ns;
+ IOR<='0';
+ WAIT FOR 60 ns;
+ data_received <= bus_data;
+ IOR<='1';
+ WAIT FOR 20 ns;
+ AEN<='1';
+ WAIT FOR 20 ns;
+ END read_bus;
+
+ PROCEDURE write_bus(address : IN integer) IS
+ variable adr : std_logic_vector(23 downto 0);
+ variable dat : std_logic_vector(7 downto 0);
+ BEGIN
+-- adr:=conv_std_logic_vector(address,24);
+-- dat:=conv_std_logic_vector(data,8);
+ AEN<='0';
+ WAIT FOR 20 ns;
+ bus_adr<=conv_std_logic_vector(address,24);
+ bus_data <= conv_std_logic_vector(data,8);
+ WAIT FOR 20 ns;
+ IOW<='0';
+ WAIT FOR 60 ns;
+ IOW<='1';
+ WAIT FOR 20 ns;
+ bus_data <= "ZZZZZZZZ";
+ AEN<='1';
+ WAIT FOR 20 ns;
+ END write_bus;
+
+ begin
+ read_bus(259);
+ data<=179;
+ write_bus(259);
+ read_bus(259);
+ wait for 100 ns;
+
+ read_bus(258);
+ data<=255;
+ write_bus(258);
+ read_bus(258);
+ wait for 100 ns;
+
+ read_bus(257);
+ data<=179;
+ write_bus(257);
+ read_bus(257);
+ wait for 100 ns;
+
+end process;
+END behavior;