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authorgalmes2004-04-28 22:28:22 +0000
committergalmes2004-04-28 22:28:22 +0000
commitd957c76ea69df920b4a7a62d37ddeb937b608ae9 (patch)
tree4ed11bf1d0cbc572ad90c8bcdb99987fed946d44 /2004/n/fpga/src/clkdiv/clk200ns.vhd
parent3f9d590956b1859ca0acd69e7690c773a4cbef4c (diff)
pwm : La pwm marche, calibrée sur du 20kHz, pour une horloge de 40M.
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+-- clk200ns.vhd :
+-- Eurobot 2004 : APB Team
+-- Auteur : Fidèle GAFAN et Pierre-André Galmes
+-- Module générateur d'horloge 1us-périodique
+--
+-- On fera attention que cette horloge repose sur la fq d'horloge du FPGA.
+-- Pour changer cette fréquence, aller voir nono_const : FREQ_CLK.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+use work.nono_const.all;
+
+--ENTITY
+entity clk200ns is
+ port (
+ RST : in std_logic;
+ CLK : in std_logic; -- 40MHz
+ CLK1USOUT : out std_logic --
+ );
+end entity;
+
+--ARCHITECTURE
+architecture RTL of clk200ns is
+ signal compt: T_OCTET;
+begin
+ process(RST,CLK)
+ begin
+ if (RST = '1') then
+ CLK1USOUT <= '0';
+ compt <= x"00";
+ elsif (CLK'event and CLK = '1') then
+ compt <= compt + x"01";
+ if (compt = x"00") then -- 30
+ CLK1USOUT <= '1';
+ else
+ CLK1USOUT <= '0';
+ if (compt = (CYCLE_CLK200NS - x"01")) then
+ compt <= x"00"; -- 30
+ end if;
+ end if;
+ end if;
+ end process;
+end RTL;