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authorgalmes2004-04-28 22:23:58 +0000
committergalmes2004-04-28 22:23:58 +0000
commit3f9d590956b1859ca0acd69e7690c773a4cbef4c (patch)
tree4f4540dcc97b53fac4ecf19aa3aff7b092693d38 /2004/n/fpga/src/clk1us/clk1us.vhd
parent7bd9395bfaaa844fcab0f45988eb95b9eec9c817 (diff)
clk1us : déplacé dans clkdiv !
Diffstat (limited to '2004/n/fpga/src/clk1us/clk1us.vhd')
-rw-r--r--2004/n/fpga/src/clk1us/clk1us.vhd47
1 files changed, 0 insertions, 47 deletions
diff --git a/2004/n/fpga/src/clk1us/clk1us.vhd b/2004/n/fpga/src/clk1us/clk1us.vhd
deleted file mode 100644
index 74fc345..0000000
--- a/2004/n/fpga/src/clk1us/clk1us.vhd
+++ /dev/null
@@ -1,47 +0,0 @@
--- clk1us.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Fidèle GAFAN et Pierre-André Galmes
--- Module générateur d'horloge 1us-périodique
---
--- On fera attention que cette horloge repose sur la fq d'horloge du FPGA.
--- Pour changer cette fréquence, aller voir nono_const : FREQ_CLK.
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-use work.nono_const.all;
-
---ENTITY
-entity clk1us is
- port (
- RST : in std_logic;
- CLK : in std_logic; --40MHz
- CLK1USOUT : out std_logic
- );
-end entity;
-
---ARCHITECTURE
-architecture RTL of clk1us is
- signal compt: T_OCTET;
-begin
- process(RST,CLK)
- begin
- if (RST = '1') then
- CLK1USOUT <= '0';
- compt <= x"00";
- elsif (CLK'event and CLK = '1') then
- compt <= compt + x"01";
- if (compt = x"00") then -- 30
- CLK1USOUT <= '1';
- else
- CLK1USOUT <= '0';
- if (compt = (FREQ_CLK - x"01")) then
- compt <= x"00"; -- 30
- end if;
- end if;
- end if;
- end process;
-end RTL;