aboutsummaryrefslogtreecommitdiff
path: root/include/libopencm3/efm32/tinygecko/lcd.yaml
blob: 0e003bd8d194a6aff65e33f878a5ed6a05934f8b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
copyright: "2012 chrysn <chrysn@fsfe.org>"
license: lgpl-3+
ingroup: EFM32TG
shortdocname: EFM32TG_LCD
shortname: LCD
longname: Liquid Crystal Display driver
baseref: d0034_efm32tg_reference_manual.pdf section 29
registers_baserefext: ".4"
templateregs:
    - name: I
      comment: Bits for the various LCD interrupt registers
      fields:
          - {name: FC, shift: 0}
    - name: SEG
      comment: Bits for the individual SEG pins
      override_backref: These values are used by the SEGDxL registers, as defined in d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21.
      fields:
          - {name: 23, shift: 23}
          - {name: 22, shift: 22}
          - {name: 21, shift: 21}
          - {name: 20, shift: 20}
          - {name: 19, shift: 19}
          - {name: 18, shift: 18}
          - {name: 17, shift: 17}
          - {name: 16, shift: 16}
          - {name: 15, shift: 15}
          - {name: 14, shift: 14}
          - {name: 13, shift: 13}
          - {name: 12, shift: 12}
          - {name: 11, shift: 11}
          - {name: 10, shift: 10}
          - {name: 9, shift: 9}
          - {name: 8, shift: 8}
          - {name: 7, shift: 7}
          - {name: 6, shift: 6}
          - {name: 5, shift: 5}
          - {name: 4, shift: 4}
          - {name: 3, shift: 3}
          - {name: 2, shift: 2}
          - {name: 1, shift: 1}
          - {name: 0, shift: 0}
registers:
    - name: CTRL
      offset: 0x000
      definition_baserefext: .5.1
      fields:
          - name: DSC
            shift: 23
          - name: UDCTRL
            shift: 1
            length: 2
            values:
                - {name: REGULAR, value: 0}
                - {name: FCEVENT, value: 1}
                - {name: FRAMESTART, value: 2}
          - name: EN
            shift: 0
    - name: DISPCTRL
      offset: 0x004
      definition_baserefext: .5.2
      fields:
          # MUXE left out and defined manually at the end
          - name: VBLEV
            shift: 18
            length: 3
            values:
                - {name: LEVEL0, value: 0}
                - {name: LEVEL1, value: 1}
                - {name: LEVEL2, value: 2}
                - {name: LEVEL3, value: 3}
                - {name: LEVEL4, value: 4}
                - {name: LEVEL5, value: 5}
                - {name: LEVEL6, value: 6}
                - {name: LEVEL7, value: 7}
          - name: VLCDSEL
            shift: 16
            values:
                - {name: VDD, value: 0}
                - {name: VEXTBOOST, value: 1}
          - name: CONCONF
            shift: 15
            values:
                - {value: 0, name: VLCD}
                - {value: 1, name: GND}
          - name: CONLEV
            shift: 8
            length: 5
            type: uint
            doc: "By this parameter, the voltage V_LCD_OUT is interpolated linearly from 0.5V_LCD to V_LCD."
            values:
                - {value: 0, name: MIN}
                - {value: 31, name: MAX}
          - name: WAVE
            shift: 4
            values:
                - {value: 0, name: LOWPOWER}
                - {value: 1, name: NORMAL}
          - name: BIAS
            shift: 2
            length: 2
            values:
                - {value: 0, name: STATIC}
                - {value: 1, name: ONEHALF}
                - {value: 2, name: ONETHIRD}
                - {value: 3, name: ONEFOURTH}
          - name: MUX
            mask: "0x00400003"
            values:
                - {value: "0x00000000", name: STATIC}
                - {value: "0x00000001", name: DUPLEX}
                - {value: "0x00000002", name: TRIPLEX}
                - {value: "0x00000003", name: QUADRUPLEX}
                - {value: "0x00400001", name: SEXTAPLEX}
                - {value: "0x00400003", name: OCTAPLEX}
            doc: These definitions munge the MUX and the MUXE fields, as they are described in the documentation only together too.
    - name: SEGEN
      offset: 0x008
      definition_baserefext: .5.3
      # FIXME how do we reperesent this best?
    - name: BACTRL
      offset: 0x00c
      definition_baserefext: .5.4
      fields:
          - name: FCTOP
            shift: 18
            length: 6
            type: uint
          - name: FCPRESC
            shift: 16
            length: 2
            values:
                - {value: 0, name: DIV1}
                - {value: 1, name: DIV2}
                - {value: 2, name: DIV4}
                - {value: 3, name: DIV8}
          - name: FCEN
            shift: 8
          - name: ALGOSEL
            shift: 7
            values:
                - {value: 0, name: AND}
                - {value: 1, name: OR}
          - name: AREGBSC
            shift: 5
            length: 2
            values: &BACTRL_AREGBSC
                - {value: 0, name: NOSHIFT}
                - {value: 1, name: SHIFTLEFT}
                - {value: 2, name: SHIFTRIGHT}
          - name: AREGASC
            shift: 3
            length: 2
            values: *BACTRL_AREGBSC
          - name: AEN
            shift: 2
          - name: BLANK
            shift: 1
          - name: BLINKEN
            shift: 0
    - name: STATUS
      offset: 0x010
      definition_baserefext: .5.5
      fields:
          - name: BLINK
            shift: 8
          - name: ASTATE
            shift: 0
            length: 4
            type: uint
    - name: AREGA
      offset: 0x014
      # FIXME: how do we represent this in the header?
    - name: AREGB
      offset: 0x018
      # FIXME: how do we represent this in the header?
    - name: IF
      offset: 0x01c
      definition_baserefext: .5.8
      fields: I
    - name: IFS
      offset: 0x020
      definition_baserefext: .5.9
      fields: I
    - name: IFC
      offset: 0x024
      definition_baserefext: .5.10
      fields: I
    - name: IEN
      offset: 0x028
      definition_baserefext: .5.11
      fields: I
    - name: SEGD0L
      offset: 0x040
      fields: SEG
    - name: SEGD1L
      offset: 0x044
      fields: SEG
    - name: SEGD2L
      offset: 0x048
      fields: SEG
    - name: SEGD3L
      offset: 0x04c
      fields: SEG
    - name: FREEZE
      offset: 0x060
      definition_baserefext: .5.16
      fields:
          - name: REGFREEZE
            shift: 0
            values:
                - {value: 0, name: UPDATE}
                - {value: 1, name: FREEZE}
      # FIXME: this seems to be a typical FREEZE register
    - name: SYNCBUSY
      offset: 0x064
      definition_baserefext: .5.17
      fields:
          - {name: SEGD7L, shift: 19}
          - {name: SEGD6L, shift: 18}
          - {name: SEGD5L, shift: 17}
          - {name: SEGD4L, shift: 16}
          - {name: SEGD3L, shift: 7}
          - {name: SEGD2L, shift: 6}
          - {name: SEGD1L, shift: 5}
          - {name: SEGD0L, shift: 4}
          - {name: AREGB, shift: 3}
          - {name: AREGA, shift: 2}
          - {name: BACTRL, shift: 1}
          - {name: CTRL, shift: 0}
    - name: SEGD4L
      offset: 0x0CC
      fields: SEG
    - name: SEGD5L
      offset: 0x0D0
      fields: SEG
    - name: SEGD6L
      offset: 0x0D4
      fields: SEG
    - name: SEGD7L
      offset: 0x0D8
      fields: SEG