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-rw-r--r--include/libopencm3/stm32/f1/dma.h38
-rw-r--r--include/libopencm3/stm32/f1/doc-stm32f1.h6
-rw-r--r--include/libopencm3/stm32/f1/gpio.h246
-rw-r--r--include/libopencm3/stm32/f1/rcc.h96
4 files changed, 321 insertions, 65 deletions
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 5aa0183..64eafe0 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_dma_defines DMA Defines
+
+@ingroup STM32F1xx_defines
+
+@brief Defined Constants and Types for the STM32F1xx DMA Controller
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -18,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
@@ -241,24 +257,39 @@
#define DMA_CCR_MEM2MEM (1 << 14)
/* PL[13:12]: Channel priority level */
+/** @defgroup dma_ch_pri DMA Channel Priority Levels
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_PL_LOW (0x0 << 12)
#define DMA_CCR_PL_MEDIUM (0x1 << 12)
#define DMA_CCR_PL_HIGH (0x2 << 12)
#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
+/**@}*/
#define DMA_CCR_PL_MASK (0x3 << 12)
#define DMA_CCR_PL_SHIFT 12
/* MSIZE[11:10]: Memory size */
+/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
+/**@}*/
#define DMA_CCR_MSIZE_MASK (0x3 << 10)
#define DMA_CCR_MSIZE_SHIFT 10
/* PSIZE[9:8]: Peripheral size */
+/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
+/**@}*/
#define DMA_CCR_PSIZE_MASK (0x3 << 8)
#define DMA_CCR_PSIZE_SHIFT 8
@@ -300,6 +331,10 @@
/* --- Generic values ------------------------------------------------------ */
+/** @defgroup dma_ch DMA Channel Number
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CHANNEL1 1
#define DMA_CHANNEL2 2
#define DMA_CHANNEL3 3
@@ -307,6 +342,7 @@
#define DMA_CHANNEL5 5
#define DMA_CHANNEL6 6
#define DMA_CHANNEL7 7
+/**@}*/
/* --- function prototypes ------------------------------------------------- */
@@ -333,3 +369,5 @@ void dma_set_memory_address(u32 dma, u8 channel, u32 address);
void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/doc-stm32f1.h b/include/libopencm3/stm32/f1/doc-stm32f1.h
index 33bae3a..04293a6 100644
--- a/include/libopencm3/stm32/f1/doc-stm32f1.h
+++ b/include/libopencm3/stm32/f1/doc-stm32f1.h
@@ -1,12 +1,14 @@
-/** @defgroup STM32F1xx_defines
+/** @defgroup STM32F1xx_defines STM32F1xx Defines
@brief Defined Constants and Types for the STM32F1xx series
@ingroup STM32F1xx
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+
@version 1.0.0
-@date 24 May 2012
+@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index e4e11be..2f4292a 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F1xx_gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,7 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
@@ -27,6 +43,10 @@
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
+/** @defgroup gpio_port_id GPIO Port IDs
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
@@ -34,8 +54,13 @@
#define GPIOE GPIO_PORT_E_BASE
#define GPIOF GPIO_PORT_F_BASE
#define GPIOG GPIO_PORT_G_BASE
+/**@}*/
/* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1)
#define GPIO2 (1 << 2)
@@ -53,6 +78,7 @@
#define GPIO14 (1 << 14)
#define GPIO15 (1 << 15)
#define GPIO_ALL 0xffff
+/**@}*/
/* --- Alternate function GPIOs -------------------------------------------- */
@@ -593,22 +619,50 @@
/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
+/** @defgroup gpio_cnf GPIO Pin Configuration
+@ingroup STM32F1xx_gpio_defines
+If mode specifies input, configuration can be
+@li Analog input
+@li Floating input
+@li Pull up/down input
+
+If mode specifies output, configuration can be
+@li Digital push-pull
+@li Digital open drain
+@li Alternate function push-pull or analog output
+@li Alternate function open drain or analog output
+@{*/
/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
+/** Analog Input */
#define GPIO_CNF_INPUT_ANALOG 0x00
+/** Digital Input Floating */
#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
+/** Digital Input Pull Up and Down */
#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
-
-/* Output mode (MODE[1:0]) values */
-#define GPIO_MODE_INPUT 0x00 /* Default */
-#define GPIO_MODE_OUTPUT_10_MHZ 0x01
-#define GPIO_MODE_OUTPUT_2_MHZ 0x02
-#define GPIO_MODE_OUTPUT_50_MHZ 0x03
-
/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
+/** Digital Output Pushpull */
#define GPIO_CNF_OUTPUT_PUSHPULL 0x00
+/** Digital Output Open Drain */
#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
+/** Alternate Function Output Pushpull */
#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
+/** Alternate Function Output Open Drain */
#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
+/**@}*/
+
+/* Pin mode (MODE[1:0]) values */
+/** @defgroup gpio_mode GPIO Pin Mode
+@ingroup STM32F1xx_gpio_defines
+@li Input (default after reset)
+@li Output mode at 10 MHz maximum speed
+@li Output mode at 2 MHz maximum speed
+@li Output mode at 50 MHz maximum speed
+@{*/
+#define GPIO_MODE_INPUT 0x00 /* Default */
+#define GPIO_MODE_OUTPUT_10_MHZ 0x01
+#define GPIO_MODE_OUTPUT_2_MHZ 0x02
+#define GPIO_MODE_OUTPUT_50_MHZ 0x03
+/**@}*/
/* --- GPIO_IDR values ----------------------------------------------------- */
@@ -652,19 +706,31 @@
/* External interrupt configuration register 4 (AFIO_EXTICR4) */
#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14)
+/* AF remap and debug I/O configuration register (AFIO_MAPR) */
+#define AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C)
+
/* --- AFIO_EVCR values ---------------------------------------------------- */
/* EVOE: Event output enable */
#define AFIO_EVCR_EVOE (1 << 7)
/* PORT[2:0]: Port selection */
+/** @defgroup afio_evcr_port EVENTOUT Port selection
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_EVCR_PORT_PA (0x0 << 4)
#define AFIO_EVCR_PORT_PB (0x1 << 4)
#define AFIO_EVCR_PORT_PC (0x2 << 4)
#define AFIO_EVCR_PORT_PD (0x3 << 4)
#define AFIO_EVCR_PORT_PE (0x4 << 4)
+/**@}*/
/* PIN[3:0]: Pin selection */
+/** @defgroup afio_evcr_pin EVENTOUT Pin selection
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
@@ -681,117 +747,206 @@
#define AFIO_EVCR_PIN_Px13 (0xD << 0)
#define AFIO_EVCR_PIN_Px14 (0xE << 0)
#define AFIO_EVCR_PIN_Px15 (0xF << 0)
+/**@}*/
/* --- AFIO_MAPR values ---------------------------------------------------- */
/* 31 reserved */
-/* PTP_PPS_REMAP: Ethernet PTP PPS remapping
+/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
+Line Devices only
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
+/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
* (only connectivity line devices) */
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
-/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
+/* TIM2ITR1_IREMAP: *//** TIM2 internal trigger 1 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
-/* SPI3_REMAP: SPI3/I2S3 remapping
+/* SPI3_REMAP: *//** SPI3/I2S3 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
+/* MII_REMAP: */ /** MII or RMII selection
+ * (only connectivity line devices) */
+#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
+
+/* CAN2_REMAP: */ /** CAN2 I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_CAN2_REMAP (1 << 22)
+
+/* ETH_REMAP: */ /** Ethernet MAC I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_ETH_REMAP (1 << 21)
+
+/**@}*/
+
/* 27 reserved */
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
+/** @defgroup afio_swj_disable Serial Wire JTAG disables
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
+/** Full Serial Wire JTAG capability */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
+/** Full Serial Wire JTAG capability without JNTRST */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
+/** JTAG-DP disabled with SW-DP enabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
+/** JTAG-DP disabled and SW-DP disabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
+/**@}*/
-/* MII_REMAP: MII or RMII selection
- * (only connectivity line devices) */
-#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
+/** @defgroup afio_remap Alternate Function Remap Controls
+@ingroup STM32F1xx_gpio_defines
-/* CAN2_REMAP: CAN2 I/O remapping
- * (only connectivity line devices) */
-#define AFIO_MAPR_CAN2_REMAP (1 << 22)
-
-/* ETH_REMAP: Ethernet MAC I/O remapping
- * (only connectivity line devices) */
-#define AFIO_MAPR_ETH_REMAP (1 << 21)
-
-/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping
+@{*/
+/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
-/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping
+/* ADC2_ETRGINJ_REMAP: */ /** ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
-/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping
+/* ADC1_ETRGREG_REMAP: */ /** ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
-/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping
+/* ADC1_ETRGINJ_REMAP: */ /** ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
-/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */
+/* TIM5CH4_IREMAP: */ /** TIM5 channel4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
-/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+/* PD01_REMAP: */ /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_MAPR_PD01_REMAP (1 << 15)
+/* TIM4_REMAP: */ /** TIM4 remapping */
+#define AFIO_MAPR_TIM4_REMAP (1 << 12)
+
+/* USART2_REMAP[1:0]: */ /** USART2 remapping */
+#define AFIO_MAPR_USART2_REMAP (1 << 3)
+
+/* USART1_REMAP[1:0]: */ /** USART1 remapping */
+#define AFIO_MAPR_USART1_REMAP (1 << 2)
+
+/* I2C1_REMAP[1:0]: */ /** I2C1 remapping */
+#define AFIO_MAPR_I2C1_REMAP (1 << 1)
+
+/* SPI1_REMAP[1:0]: */ /** SPI1 remapping */
+#define AFIO_MAPR_SPI1_REMAP (1 << 0)
+/**@}*/
+
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
+/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
-
-/* TIM4_REMAP: TIM4 remapping */
-#define AFIO_MAPR_TIM4_REMAP (1 << 12)
+/**@}*/
/* TIM3_REMAP[1:0]: TIM3 remapping */
+/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
+/**@}*/
/* TIM2_REMAP[1:0]: TIM2 remapping */
+/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
+/**@}*/
/* TIM1_REMAP[1:0]: TIM1 remapping */
+/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
+/**@}*/
/* USART3_REMAP[1:0]: USART3 remapping */
+/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
+/**@}*/
-/* USART2_REMAP[1:0]: USART2 remapping */
-#define AFIO_MAPR_USART2_REMAP (1 << 3)
+/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
+@ingroup STM32F1xx_gpio_defines
-/* USART1_REMAP[1:0]: USART1 remapping */
-#define AFIO_MAPR_USART1_REMAP (1 << 2)
+@{*/
+/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
+#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10)
-/* I2C1_REMAP[1:0]: I2C1 remapping */
-#define AFIO_MAPR_I2C1_REMAP (1 << 1)
+/* TIM14_REMAP: */ /** TIM14 remapping */
+#define AFIO_MAPR2_TIM14_REMAP (1 << 9)
-/* SPI1_REMAP[1:0]: SPI1 remapping */
-#define AFIO_MAPR_SPI1_REMAP (1 << 0)
+/* TIM13_REMAP: */ /** TIM13 remapping */
+#define AFIO_MAPR2_TIM13_REMAP (1 << 8)
+
+/* TIM11_REMAP: */ /** TIM11 remapping */
+#define AFIO_MAPR2_TIM11_REMAP (1 << 7)
+
+/* TIM10_REMAP: */ /** TIM10 remapping */
+#define AFIO_MAPR2_TIM10_REMAP (1 << 6)
+
+/* TIM9_REMAP: */ /** TIM9 remapping */
+#define AFIO_MAPR2_TIM9_REMAP (1 << 5)
+
+/**@}*/
/* --- AFIO_EXTICR1 values ------------------------------------------------- */
/* --- AFIO_EXTICR2 values ------------------------------------------------- */
/* --- AFIO_EXTICR3 values ------------------------------------------------- */
/* --- AFIO_EXTICR4 values ------------------------------------------------- */
-/* EXTI0 - EXTI15 interrupt source selection registers */
-
-/* Note: For using them we should define a function that calculates the right
- * registers, using definitions is probably not a good idea.
- */
+/** @defgroup afio_exti Alternate Function EXTI pin number
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
+
+#define AFIO_EXTI0 0
+#define AFIO_EXTI1 1
+#define AFIO_EXTI2 2
+#define AFIO_EXTI3 3
+#define AFIO_EXTI4 4
+#define AFIO_EXTI5 5
+#define AFIO_EXTI6 6
+#define AFIO_EXTI7 7
+#define AFIO_EXTI8 8
+#define AFIO_EXTI9 9
+#define AFIO_EXTI10 10
+#define AFIO_EXTI11 11
+#define AFIO_EXTI12 12
+#define AFIO_EXTI13 13
+#define AFIO_EXTI14 14
+#define AFIO_EXTI15 15
+
+/**@}*/
/* --- Function prototypes ------------------------------------------------- */
@@ -803,5 +958,10 @@ void gpio_toggle(u32 gpioport, u16 gpios);
u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
+void gpio_set_eventout(u8 evoutport, u8 evoutpin);
+void gpio_primary_remap(u8 swjenable, u32 maps);
+void gpio_secondary_remap(u32 maps);
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h
index 0477e15..63f6770 100644
--- a/include/libopencm3/stm32/f1/rcc.h
+++ b/include/libopencm3/stm32/f1/rcc.h
@@ -1,27 +1,18 @@
-/** @file
-
-@ingroup STM32F1xx
+/** @defgroup STM32F1xx_rcc_defines RCC Defines
@brief <b>libopencm3 STM32F1xx Reset and Clock Control</b>
+@ingroup STM32F1xx_defines
+
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
-@date 18 May 2012
+@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
-/** @defgroup STM32F1xx_rcc_defines
-
-@brief Defined Constants and Types for the STM32F1xx Reset and Clock Control
-
-@ingroup STM32F1xx_defines
-
-LGPL License Terms @ref lgpl_license
-
- */
/*
* This file is part of the libopencm3 project.
*
@@ -41,6 +32,7 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
#ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H
@@ -86,6 +78,10 @@ LGPL License Terms @ref lgpl_license
/* --- RCC_CFGR values ----------------------------------------------------- */
/* MCO: Microcontroller clock output */
+/** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_MCO_NOCLK 0x0
#define RCC_CFGR_MCO_SYSCLK 0x4
#define RCC_CFGR_MCO_HSICLK 0x5
@@ -95,16 +91,26 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
#define RCC_CFGR_MCO_XT1 0xa /* (**) */
#define RCC_CFGR_MCO_PLL3 0xb /* (**) */
+/**@}*/
/* USBPRE: USB prescaler (RCC_CFGR[22]) */
+/** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
+/**@}*/
/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1
/* PLLMUL: PLL multiplication factor */
+/** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
@@ -122,38 +128,69 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
+/**@}*/
/* TODO: conn. line differs. */
/* PLLXTPRE: HSE divider for PLL entry */
+/** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
+/**@}*/
/* PLLSRC: PLL entry clock source */
+/** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */
+/**@}*/
/* ADCPRE: ADC prescaler */
+/****************************************************************************/
+/** @defgroup rcc_cfgr_adcpre RCC ADC Clock Prescaler enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
+/**@}*/
/* PPRE2: APB high-speed prescaler (APB2) */
+/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
+/**@}*/
/* PPRE1: APB low-speed prescaler (APB1) */
+/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
+/**@}*/
/* HPRE: AHB prescaler */
+/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
@@ -163,6 +200,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
+/**@}*/
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
@@ -170,9 +208,14 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
/* SW: System clock switch */
+/** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
+/**@}*/
/* --- RCC_CIR values ------------------------------------------------------ */
@@ -211,6 +254,10 @@ LGPL License Terms @ref lgpl_license
/* --- RCC_APB2RSTR values ------------------------------------------------- */
+/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */
#define RCC_APB2RSTR_USART1RST (1 << 14)
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */
@@ -226,9 +273,14 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB2RSTR_IOPBRST (1 << 3)
#define RCC_APB2RSTR_IOPARST (1 << 2)
#define RCC_APB2RSTR_AFIORST (1 << 0)
+/**@}*/
/* --- RCC_APB1RSTR values ------------------------------------------------- */
+/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB1RSTR_DACRST (1 << 29)
#define RCC_APB1RSTR_PWRRST (1 << 28)
#define RCC_APB1RSTR_BKPRST (1 << 27)
@@ -251,6 +303,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1RSTR_TIM4RST (1 << 2)
#define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0)
+/**@}*/
/* --- RCC_AHBENR values --------------------------------------------------- */
@@ -269,7 +322,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_AHBENR_SRAMEN (1 << 2)
#define RCC_AHBENR_DMA2EN (1 << 1)
#define RCC_AHBENR_DMA1EN (1 << 0)
-/*@}*/
+/**@}*/
/* --- RCC_APB2ENR values -------------------------------------------------- */
@@ -292,7 +345,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB2ENR_IOPBEN (1 << 3)
#define RCC_APB2ENR_IOPAEN (1 << 2)
#define RCC_APB2ENR_AFIOEN (1 << 0)
-/*@}*/
+/**@}*/
/* --- RCC_APB1ENR values -------------------------------------------------- */
@@ -322,7 +375,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1ENR_TIM4EN (1 << 2)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
-/*@}*/
+/**@}*/
/* --- RCC_BDCR values ----------------------------------------------------- */
@@ -347,8 +400,13 @@ LGPL License Terms @ref lgpl_license
/* --- RCC_AHBRSTR values -------------------------------------------------- */
+/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_AHBRSTR_ETHMACRST (1 << 14)
#define RCC_AHBRSTR_OTGFSRST (1 << 12)
+/**@}*/
/* --- RCC_CFGR2 values ---------------------------------------------------- */
@@ -447,10 +505,6 @@ void rcc_set_usbpre(u32 usbpre);
u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_in_hsi_out_64mhz(void);
void rcc_clock_setup_in_hsi_out_48mhz(void);
-
-/**
- * Maximum speed possible for F100 (Value Line) on HSI
- */
void rcc_clock_setup_in_hsi_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
@@ -459,3 +513,5 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
#endif
+/**@}*/
+