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Diffstat (limited to 'include/libopencm3/lpc43xx/cgu.h')
-rw-r--r--include/libopencm3/lpc43xx/cgu.h84
1 files changed, 42 insertions, 42 deletions
diff --git a/include/libopencm3/lpc43xx/cgu.h b/include/libopencm3/lpc43xx/cgu.h
index bf2967a..1234834 100644
--- a/include/libopencm3/lpc43xx/cgu.h
+++ b/include/libopencm3/lpc43xx/cgu.h
@@ -18,7 +18,7 @@
*/
#ifndef LPC43XX_CGU_H
-#define LPC43XX_CGU_H
+#define CGU_LPC43XX_CGU_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
@@ -41,126 +41,126 @@
#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)
/* PLL0USB N/P-divider register */
-#define PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)
+#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)
/* PLL0AUDIO status register */
-#define PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)
+#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)
/* PLL0AUDIO control register */
-#define PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)
+#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)
/* PLL0AUDIO M-divider register */
-#define PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)
+#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)
/* PLL0AUDIO N/P-divider register */
-#define PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)
+#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)
/* PLL0AUDIO fractional divider register */
-#define PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)
+#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)
/* PLL1 status register */
-#define PLL1_STAT MMIO32(CGU_BASE + 0x040)
+#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)
/* PLL1 control register */
-#define PLL1_CTRL MMIO32(CGU_BASE + 0x044)
+#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)
/* Integer divider A control register */
-#define IDIVA_CTRL MMIO32(CGU_BASE + 0x048)
+#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)
/* Integer divider B control register */
-#define IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)
+#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)
/* Integer divider C control register */
-#define IDIVC_CTRL MMIO32(CGU_BASE + 0x050)
+#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)
/* Integer divider D control register */
-#define IDIVD_CTRL MMIO32(CGU_BASE + 0x054)
+#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)
/* Integer divider E control register */
-#define IDIVE_CTRL MMIO32(CGU_BASE + 0x058)
+#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)
/* Output stage 0 control register */
-#define BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)
+#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)
/* Output stage 1 control register for base clock */
-#define BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)
+#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)
/* Output stage 2 control register for base clock */
-#define BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)
+#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)
/* Output stage 3 control register for base clock */
-#define BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)
+#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)
/* Output stage 4 control register for base clock */
-#define BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)
+#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)
/* Output stage 5 control register for base clock */
-#define BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)
+#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)
/* Output stage 6 control register for base clock */
-#define BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)
+#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)
/* Output stage 7 control register for base clock */
-#define BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)
+#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)
/* Output stage 8 control register for base clock */
-#define BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)
+#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)
/* Output stage 9 control register for base clock */
-#define BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)
+#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)
/* Output stage 10 control register for base clock */
-#define BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)
+#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)
/* Output stage 11 control register for base clock */
-#define BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)
+#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)
/* Output stage 12 control register for base clock */
-#define BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)
+#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)
/* Output stage 13 control register for base clock */
-#define BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)
+#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)
/* Output stage 14 control register for base clock */
-#define BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)
+#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)
/* Output stage 15 control register for base clock */
-#define BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)
+#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)
/* Output stage 16 control register for base clock */
-#define BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)
+#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)
/* Output stage 17 control register for base clock */
-#define BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)
+#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)
/* Output stage 18 control register for base clock */
-#define BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)
+#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)
/* Output stage 19 control register for base clock */
-#define BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)
+#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)
/* Output stage 20 control register for base clock */
-#define BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)
+#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)
/* Reserved output stage */
-#define OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)
+#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)
/* Reserved output stage */
-#define OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)
+#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)
/* Reserved output stage */
-#define OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)
+#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)
/* Reserved output stage */
-#define OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)
+#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)
/* Output stage 25 control register for base clock */
-#define BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)
+#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)
/* Output stage 26 control CLK register for base clock */
-#define BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)
+#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)
/* Output stage 27 control CLK register for base clock */
-#define BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
+#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
#endif