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-rw-r--r--examples/stm32/f1/stm32-h103/timer/timer.c183
1 files changed, 183 insertions, 0 deletions
diff --git a/examples/stm32/f1/stm32-h103/timer/timer.c b/examples/stm32/f1/stm32-h103/timer/timer.c
new file mode 100644
index 0000000..48cae12
--- /dev/null
+++ b/examples/stm32/f1/stm32-h103/timer/timer.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/f1/rcc.h>
+#include <libopencm3/stm32/f1/gpio.h>
+#include <libopencm3/stm32/timer.h>
+#include <libopencm3/stm32/nvic.h>
+#include <libopencm3/stm32/exti.h>
+
+u16 frequency_sequence[18] = {
+ 1000,
+ 500,
+ 1000,
+ 500,
+ 1000,
+ 500,
+ 2000,
+ 500,
+ 2000,
+ 500,
+ 2000,
+ 500,
+ 1000,
+ 500,
+ 1000,
+ 500,
+ 1000,
+ 5000
+};
+
+
+int frequency_sel = 0;
+
+u16 compare_time;
+u16 new_time;
+u16 frequency;
+int debug = 0;
+
+void clock_setup(void)
+{
+ rcc_clock_setup_in_hse_8mhz_out_72mhz();
+
+}
+
+void gpio_setup(void)
+{
+ /* Enable GPIOC clock. */
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN);
+
+ /*
+ * Set GPIO12 (PORTC) (led) to
+ * 'output alternate function push-pull'.
+ */
+ gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
+
+ gpio_set(GPIOC, GPIO12);
+
+}
+
+void tim_setup(void)
+{
+
+ /* Enable TIM2 clock. */
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
+
+
+ /* Enable TIM2 interrupt. */
+ nvic_enable_irq(NVIC_TIM2_IRQ);
+
+ /* Reset TIM2 peripheral */
+ timer_reset(TIM2);
+
+ /* Timer global mode:
+ * - No divider
+ * - alignment edge
+ * - direction up
+ */
+ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
+ TIM_CR1_CMS_EDGE,
+ TIM_CR1_DIR_UP);
+
+ /* Reset prescaler value. */
+ timer_set_prescaler(TIM2, 36000);
+
+ /* Enable preload. */
+ timer_disable_preload(TIM2);
+
+ /* Continous mode. */
+ timer_continuous_mode(TIM2);
+
+ /* Period (36kHz) */
+ timer_set_period(TIM2, 65535);
+
+ /* Disable outputs. */
+ timer_disable_oc_output(TIM2, TIM_OC1);
+ timer_disable_oc_output(TIM2, TIM_OC2);
+ timer_disable_oc_output(TIM2, TIM_OC3);
+ timer_disable_oc_output(TIM2, TIM_OC4);
+
+ /* -- OC1 configuration -- */
+
+ /* Configure global mode of line 1. */
+ timer_disable_oc_clear(TIM2, TIM_OC1);
+ timer_disable_oc_preload(TIM2, TIM_OC1);
+ timer_set_oc_slow_mode(TIM2, TIM_OC1);
+ timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
+
+ /* Set the capture compare value for OC1. */
+ timer_set_oc_value(TIM2, TIM_OC1, 1000);
+
+ /* ---- */
+ /* ARR reload enable */
+ timer_disable_preload(TIM2);
+
+ /* Counter enable */
+ timer_enable_counter(TIM2);
+
+ /* Enable commutation interrupt */
+ timer_enable_irq(TIM2, TIM_DIER_CC1IE);
+}
+
+void tim2_isr(void)
+{
+
+ if (timer_get_flag(TIM2, TIM_SR_CC1IF)) {
+
+ /* Clear compare interrupt flag. */
+ timer_clear_flag(TIM2, TIM_SR_CC1IF);
+
+ /*
+ * Get current timer value to calculate next
+ * compare register value
+ */
+ compare_time = timer_get_counter(TIM2);
+
+ /*
+ * Calculate and set the next compare value.
+ */
+ frequency = frequency_sequence[frequency_sel++];
+ new_time = compare_time + frequency;
+
+ timer_set_oc_value(TIM2, TIM_OC1,
+ new_time);
+ if (frequency_sel == 18) {
+ frequency_sel = 0;
+ }
+
+ /* Toggle led to indicate compare event */
+ gpio_toggle(GPIOC, GPIO12);
+
+ }
+}
+
+int main(void)
+{
+
+ clock_setup();
+ gpio_setup();
+ tim_setup();
+
+ while (1) {
+ __asm("nop");
+ }
+
+ return 0;
+}