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-rw-r--r--examples/stm32/lisa-m/fancyblink/fancyblink.c2
-rw-r--r--lib/stm32/rcc.c54
2 files changed, 55 insertions, 1 deletions
diff --git a/examples/stm32/lisa-m/fancyblink/fancyblink.c b/examples/stm32/lisa-m/fancyblink/fancyblink.c
index efada62..5987bdf 100644
--- a/examples/stm32/lisa-m/fancyblink/fancyblink.c
+++ b/examples/stm32/lisa-m/fancyblink/fancyblink.c
@@ -24,7 +24,7 @@
/* Set STM32 to 72 MHz. */
void clock_setup(void)
{
- rcc_clock_setup_in_hse_16mhz_out_72mhz();
+ rcc_clock_setup_in_hse_12mhz_out_72mhz();
/* Enable GPIOC clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
diff --git a/lib/stm32/rcc.c b/lib/stm32/rcc.c
index f429ff4..5869c83 100644
--- a/lib/stm32/rcc.c
+++ b/lib/stm32/rcc.c
@@ -531,6 +531,60 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
}
+void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
+{
+ /* Enable internal high-speed oscillator. */
+ rcc_osc_on(HSI);
+ rcc_wait_for_osc_ready(HSI);
+
+ /* Select HSI as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
+
+ /* Enable external high-speed oscillator 16MHz. */
+ rcc_osc_on(HSE);
+ rcc_wait_for_osc_ready(HSE);
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
+
+ /*
+ * Set prescalers for AHB, ADC, ABP1, ABP2.
+ * Do this before touching the PLL (TODO: why?).
+ */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
+
+ /*
+ * Sysclk runs with 72MHz -> 2 waitstates.
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+ flash_set_ws(FLASH_LATENCY_2WS);
+
+ /*
+ * Set the PLL multiplication factor to 9.
+ * 12MHz (external) * 6 (multiplier) / 1 (PLLXTPRE_HSE_CLK) = 72MHz
+ */
+ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6);
+
+ /* Select HSI as PLL source. */
+ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
+
+ /*
+ * Divide external frequency by 2 before entering PLL
+ * (only valid/needed for HSE).
+ */
+ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
+
+ /* Enable PLL oscillator and wait for it to stabilize. */
+ rcc_osc_on(PLL);
+ rcc_wait_for_osc_ready(PLL);
+
+ /* Select PLL as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+}
+
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */