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authorUwe Hermann2011-02-09 01:56:53 +0100
committerUwe Hermann2011-02-09 02:48:51 +0100
commit0a0ce22762136f0a65af13ea2e160913c6af8767 (patch)
tree9efafff9d90e886dd2f2f4d386d103c6db7982fe /lib/stm32
parente0a488f586abd24c8b3448ceb0fc94a10c572cc0 (diff)
Add rcc_clock_setup_in_hse_8mhz_out_24mhz().
Thanks Marko Kraljevic <krasnaya.zvezda@gmail.com> for the patch!
Diffstat (limited to 'lib/stm32')
-rw-r--r--lib/stm32/rcc.c53
1 files changed, 53 insertions, 0 deletions
diff --git a/lib/stm32/rcc.c b/lib/stm32/rcc.c
index 997163a..f429ff4 100644
--- a/lib/stm32/rcc.c
+++ b/lib/stm32/rcc.c
@@ -424,6 +424,59 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
}
+void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
+{
+ /* Enable internal high-speed oscillator. */
+ rcc_osc_on(HSI);
+ rcc_wait_for_osc_ready(HSI);
+
+ /* Select HSI as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
+
+ /* Enable external high-speed oscillator 8MHz. */
+ rcc_osc_on(HSE);
+ rcc_wait_for_osc_ready(HSE);
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
+
+ /*
+ * Set prescalers for AHB, ADC, ABP1, ABP2.
+ * Do this before touching the PLL (TODO: why?).
+ */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
+
+ /*
+ * Sysclk runs with 24MHz -> 0 waitstates.
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+ flash_set_ws(FLASH_LATENCY_0WS);
+
+ /*
+ * Set the PLL multiplication factor to 3.
+ * 8MHz (external) * 3 (multiplier) = 24MHz
+ */
+ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL3);
+
+ /* Select HSE as PLL source. */
+ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
+
+ /*
+ * External frequency undivided before entering PLL
+ * (only valid/needed for HSE).
+ */
+ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
+
+ /* Enable PLL oscillator and wait for it to stabilize. */
+ rcc_osc_on(PLL);
+ rcc_wait_for_osc_ready(PLL);
+
+ /* Select PLL as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+}
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */