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authorUwe Hermann2011-11-11 21:43:03 +0100
committerUwe Hermann2011-11-11 21:43:41 +0100
commitb05eff8dbff13a89d122be57aa53eff9fd9ce515 (patch)
tree2077d8ff2beab4b57013a7b36b093b7cd19d3210 /include
parentdb3c0870bb09db792e7e8fb735233a0e2ebf4e8d (diff)
stm32/f2/pwr.h: Document reserved bits.
Diffstat (limited to 'include')
-rw-r--r--include/libopencm3/stm32/f2/pwr.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/include/libopencm3/stm32/f2/pwr.h b/include/libopencm3/stm32/f2/pwr.h
index 7cf8dab..2ff1d34 100644
--- a/include/libopencm3/stm32/f2/pwr.h
+++ b/include/libopencm3/stm32/f2/pwr.h
@@ -23,18 +23,24 @@
#include <libopencm3/stm32/pwr.h>
/*
- * This file extends the version in stm_common with definitions only
+ * This file extends the common STM32 version with definitions only
* applicable to the STM32F2 series of devices.
*/
/* --- PWR_CR values ------------------------------------------------------- */
-/* FPDS: Flash power down in stop mode, only available in F2 family devices. */
+/* Bits [31:10]: Reserved, always read as 0. */
+
+/* FPDS: Flash power down in stop mode */
#define PWR_CR_FPDS (1 << 9)
/* --- PWR_CSR values ------------------------------------------------------ */
+/* Bits [31:10]: Reserved, always read as 0. */
+
/* BRE: Backup regulator enable */
#define PWR_CSR_BRE (1 << 9)
+/* Bits [7:4]: Reserved, always read as 0. */
+
#endif