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authorFergus Noble2011-09-14 13:47:33 -0700
committerFergus Noble2011-09-14 13:47:33 -0700
commitaf64b76bd6b89488f0cd1ad1a899367d6a28f655 (patch)
tree51eadfe8534f56c6e7fe6039853bf26f7fa4de19 /include/libopencm3/stm32/f2
parent87d4045c22d75143ed8f750c184966eeba55a3b6 (diff)
Restructuring stm32 include directories.
Diffstat (limited to 'include/libopencm3/stm32/f2')
-rw-r--r--include/libopencm3/stm32/f2/memorymap.h131
-rw-r--r--include/libopencm3/stm32/f2/pwr.h40
-rw-r--r--include/libopencm3/stm32/f2/spi.h42
-rw-r--r--include/libopencm3/stm32/f2/timer.h54
-rw-r--r--include/libopencm3/stm32/f2/usart.h35
5 files changed, 302 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/f2/memorymap.h b/include/libopencm3/stm32/f2/memorymap.h
new file mode 100644
index 0000000..9fe77fa
--- /dev/null
+++ b/include/libopencm3/stm32/f2/memorymap.h
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+/* --- STM32F20x specific peripheral definitions ------------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE 0x40000000
+#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
+#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
+#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
+#define PERIPH_BASE_AHB2 0x50000000
+#define PERIPH_BASE_AHB3 0x60000000
+
+/* Register boundary addresses */
+
+/* APB1 */
+#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
+#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
+#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
+#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
+#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
+#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
+#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
+#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
+#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
+/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
+#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
+#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
+#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
+/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
+#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
+#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
+/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
+#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
+#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
+#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
+#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
+#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
+#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
+#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)
+/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */
+#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
+#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
+/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
+#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
+#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
+
+/* APB2 */
+#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)
+#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)
+/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */
+#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)
+#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
+/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
+#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
+#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000)
+#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000)
+/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
+#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2800)
+/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
+#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
+/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */
+#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)
+#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)
+#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)
+#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)
+#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)
+/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */
+
+/* AHB1 */
+#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)
+#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)
+#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)
+#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)
+#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)
+#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)
+#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)
+#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)
+#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)
+/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */
+#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
+/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
+#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)
+#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)
+#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)
+/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */
+#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)
+#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)
+/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */
+#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)
+/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */
+#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)
+/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */
+
+/* AHB2 */
+#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000)
+/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
+#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
+/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5006 07FF): Reserved */
+#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
+/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
+
+/* AHB3 */
+#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000)
+
+/* PPIB */
+#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
+
+#endif
diff --git a/include/libopencm3/stm32/f2/pwr.h b/include/libopencm3/stm32/f2/pwr.h
new file mode 100644
index 0000000..7cf8dab
--- /dev/null
+++ b/include/libopencm3/stm32/f2/pwr.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_PWR_F2_H
+#define LIBOPENCM3_PWR_F2_H
+
+#include <libopencm3/stm32/pwr.h>
+
+/*
+ * This file extends the version in stm_common with definitions only
+ * applicable to the STM32F2 series of devices.
+ */
+
+/* --- PWR_CR values ------------------------------------------------------- */
+
+/* FPDS: Flash power down in stop mode, only available in F2 family devices. */
+#define PWR_CR_FPDS (1 << 9)
+
+/* --- PWR_CSR values ------------------------------------------------------ */
+
+/* BRE: Backup regulator enable */
+#define PWR_CSR_BRE (1 << 9)
+
+#endif
diff --git a/include/libopencm3/stm32/f2/spi.h b/include/libopencm3/stm32/f2/spi.h
new file mode 100644
index 0000000..62550cf
--- /dev/null
+++ b/include/libopencm3/stm32/f2/spi.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_F2_H
+#define LIBOPENCM3_SPI_F2_H
+
+#include <libopencm3/stm32/spi.h>
+
+/*
+ * This file extends the version in stm_common with definitions only
+ * applicable to the STM32F2 series of devices.
+ */
+
+/* --- SPI_CR2 values ------------------------------------------------------ */
+
+/* FRF: Frame format. */
+#define SPI_CR2_FRF (1 << 4)
+#define SPI_CR2_FRF_TI (1 << 4)
+#define SPI_CR2_FRF_MOTOROLA (1 << 4)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* TIFRFE: TI frame format error. */
+#define SPI_SR_RXNE (1 << 0)
+
+#endif
diff --git a/include/libopencm3/stm32/f2/timer.h b/include/libopencm3/stm32/f2/timer.h
new file mode 100644
index 0000000..f7c82ae
--- /dev/null
+++ b/include/libopencm3/stm32/f2/timer.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_TIMER_F2_H
+#define LIBOPENCM3_TIMER_F2_H
+
+#include <libopencm3/stm32/timer.h>
+
+
+/*
+ * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
+ * CNT, ARR, CCR1, CCR2, CCR3, CCR4
+ */
+
+/* Timer 2/5 option register (TIMx_OR) */
+#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
+#define TIM2_OR TIM_OR(TIM2)
+#define TIM5_OR TIM_OR(TIM5)
+
+/* --- TIM2_OR values ---------------------------------------------------- */
+
+/* MOE: Main output enable */
+#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
+#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
+#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
+#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
+#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
+
+/* --- TIM5_OR values ---------------------------------------------------- */
+
+/* MOE: Main output enable */
+#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
+#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
+#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
+#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
+#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
+
+#endif
diff --git a/include/libopencm3/stm32/f2/usart.h b/include/libopencm3/stm32/f2/usart.h
new file mode 100644
index 0000000..1baf5a1
--- /dev/null
+++ b/include/libopencm3/stm32/f2/usart.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USART_F2_H
+#define LIBOPENCM3_USART_F2_H
+
+#include <libopencm3/stm32/usart.h>
+
+/* --- USART_CR1 values ---------------------------------------------------- */
+
+/* OVER8: Oversampling mode */
+#define USART_CR1_OVER8 (1 << 15)
+
+/* --- USART_CR3 values ---------------------------------------------------- */
+
+/* ONEBIT: One sample bit method enable */
+#define USART_CR3_ONEBIT (1 << 11)
+
+#endif