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authorMichael Ossmann2012-05-22 10:38:49 -0600
committerMichael Ossmann2012-05-22 10:38:49 -0600
commit95224dbc5e47d7afed39192feb00fc9f2caa9a32 (patch)
tree04fa6c5618408d1e34e60dab0c0d47204a5ac7bf /include/libopencm3/lpc43xx/memorymap.h
parentba35602e3dfe846b1aa905c72e3d5055ab924945 (diff)
finished gpio.h and memorymap.h changes for LPC43xx but still much to fill in
Diffstat (limited to 'include/libopencm3/lpc43xx/memorymap.h')
-rw-r--r--include/libopencm3/lpc43xx/memorymap.h111
1 files changed, 77 insertions, 34 deletions
diff --git a/include/libopencm3/lpc43xx/memorymap.h b/include/libopencm3/lpc43xx/memorymap.h
index 1114442..52efd2c 100644
--- a/include/libopencm3/lpc43xx/memorymap.h
+++ b/include/libopencm3/lpc43xx/memorymap.h
@@ -2,6 +2,7 @@
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -17,49 +18,91 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LPC17XX_MEMORYMAP_H
-#define LPC17XX_MEMORYMAP_H
+#ifndef LPC43XX_MEMORYMAP_H
+#define LPC43XX_MEMORYMAP_H
#include <libopencm3/cm3/common.h>
-/* --- LPC17XX specific peripheral definitions ----------------------------- */
+/* --- LPC43XX specific peripheral definitions ----------------------------- */
/* Memory map for all busses */
-#define PERIPH_BASE_APB0 0x40000000
-#define PERIPH_BASE_APB1 0x40080000
-#define PERIPH_BASE_AHB 0x20000000
+#define PERIPH_BASE_AHB 0x40000000
+#define PERIPH_BASE_APB0 0x40080000
+#define PERIPH_BASE_APB1 0x400A0000
+#define PERIPH_BASE_APB2 0x400C0000
+#define PERIPH_BASE_APB3 0x400E0000
/* Register boundary addresses */
+/* AHB */
+#define SCT_BASE (PERIPH_BASE_AHB + 0x00000)
+/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
+#define DMA_BASE (PERIPH_BASE_AHB + 0x02000)
+#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)
+#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000)
+#define EMC_BASE (PERIPH_BASE_AHB + 0x05000)
+#define USB0_BASE (PERIPH_BASE_AHB + 0x06000)
+#define USB1_BASE (PERIPH_BASE_AHB + 0x07000)
+#define LCD_BASE (PERIPH_BASE_AHB + 0x08000)
+/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */
+#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
+
+/* 0x4001 2000 - 0x4003 FFFF Reserved */
+
+/* RTC domain peripherals */
+//TODO
+
+/* clocking/reset control peripherals */
+//TODO
+
+/* 0x4006 0000 - 0x4007 FFFF Reserved */
+
/* APB0 */
-#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000)
-#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
-#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000)
-#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000)
-#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000)
-/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */
-#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000)
-#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
-#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
-#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
-#define GPIOINTERRPUT_BASE (PERIPH_BASE_APB0 + 0x28000)
-#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
-#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
-#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)
-#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000)
-#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000)
-#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000)
-#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000)
-#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000)
-/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */
-#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000)
-/* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */
+#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)
+#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000)
+#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000)
+#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)
+#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
+#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)
+#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000)
+#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)
+#define GPIO_GROUP0_INTRRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)
+#define GPIO_GROUP1_INTRRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)
-/* AHB */
-#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000)
-#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020)
-#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040)
-#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060)
-#define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080)
+/* 0x4009 0000 - 0x4009 FFFF Reserved */
+
+/* APB1 */
+//TODO
+
+/* 0x400B 0000 - 0x400B FFFF Reserved */
+
+/* APB2 */
+//TODO
+
+/* 0x400D 0000 - 0x400D FFFF Reserved */
+
+/* APB3 */
+//TODO
+
+/* 0x400F 0000 - 0x400F 0FFF Reserved */
+
+#define AES_BASE 0x400F1000
+
+/* 0x400F 2000 - 0x400F 3FFF Reserved */
+
+#define GPIO_PORT_BASE 0x400F4000
+
+/* 0x400F 8000 - 0x400F FFFF Reserved */
+
+#define SPI_PORT_BASE 0x40100000
+#define SGPIO_PORT_BASE 0x40101000
+
+/* 0x4010 2000 - 0x41FF FFFF Reserved */
+
+/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */
+
+/* 0x4400 0000 - 0x5FFF FFFF Reserved */
+
+/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */
#endif