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authorUwe Hermann2010-12-31 18:18:39 +0100
committerUwe Hermann2010-12-31 18:18:39 +0100
commit8f251e8a9d46634be4741f7f1aef3d52fb1b7dba (patch)
treefb3c17756e0b18fe19ca28f0f67b2ae636cac807 /include/libopencm3/cm3/memorymap.h
parent95793aa6cedeef06db9592602ecf3dc00edec610 (diff)
Some more file/path restructuring.
All #includes now explicitly use the "<libopencm3/stm32/rcc.h>" format. If you want to get rid of the "libopencm3" prefix in your local project you can add a respective -I entry in your Makefile (not recommended though). All .ld files and .a libs are installed in $(TOOLCHAIN_DIR)/lib directly (as before), but are now renamed to avoid potential conflicts now or in the future. Examples: libopencm3_lpc13xx.a libopencm3_lpc13xx.ld libopencm3_stm32.a libopencm3_stm32.ld
Diffstat (limited to 'include/libopencm3/cm3/memorymap.h')
-rw-r--r--include/libopencm3/cm3/memorymap.h58
1 files changed, 58 insertions, 0 deletions
diff --git a/include/libopencm3/cm3/memorymap.h b/include/libopencm3/cm3/memorymap.h
new file mode 100644
index 0000000..6f8b49d
--- /dev/null
+++ b/include/libopencm3/cm3/memorymap.h
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CM3_MEMORYMAP_H
+#define CM3_MEMORYMAP_H
+
+/* --- ARM Cortex-M3 specific definitions ---------------------------------- */
+
+/* Private peripheral bus - Internal */
+#define PPBI_BASE 0xE0000000
+#define ITM_BASE (PPBI_BASE + 0x0000)
+#define DWT_BASE (PPBI_BASE + 0x1000)
+#define FPB_BASE (PPBI_BASE + 0x2000)
+/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
+#define SCS_BASE (PPBI_BASE + 0xE000)
+/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
+
+/* --- ITM: Instrumentation Trace Macrocell --- */
+/* TODO */
+
+/* --- DWT: Data Watchpoint and Trace unit --- */
+/* TODO */
+
+/* --- FPB: Flash Patch and Breakpoint unit --- */
+/* TODO */
+
+/* --- SCS: System Control Space --- */
+
+/* ITR: Interrupt Type Register */
+#define ITR_BASE (SCS_BASE + 0x0000)
+/* SYS_TICK: System Timer */
+#define SYS_TICK_BASE (SCS_BASE + 0x0010)
+/* NVIC: Nested Vector Interrupt Controller */
+#define NVIC_BASE (SCS_BASE + 0x0100)
+/* SCB: System Control Block */
+#define SCB_BASE (SCS_BASE + 0x0D00)
+/* STE: Software Trigger Interrupt Register */
+#define STIR_BASE (SCS_BASE + 0x0F00)
+/* ID: ID space */
+#define ID_BASE (SCS_BASE + 0x0FD0)
+
+#endif