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authorTitanMKD2012-06-06 00:30:25 +0200
committerTitanMKD2012-06-06 00:30:25 +0200
commit8adc873e843ea8599e7e658d00b66bebe86c2f62 (patch)
tree0006fc458fc9cfc887ba129501da2f667722f92a /examples
parent416f633dbb5bdf8a7ef99e52f9de1142d126c8e5 (diff)
Fixed SSP, tested with Oscilloscope Write work fine (tested SPI Mode).
For more details on tests see ssp/README.
Diffstat (limited to 'examples')
-rw-r--r--examples/lpc43xx/hackrf-jellybean/ssp/README28
-rw-r--r--examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c25
2 files changed, 42 insertions, 11 deletions
diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/README b/examples/lpc43xx/hackrf-jellybean/ssp/README
index 9b43214..5354a53 100644
--- a/examples/lpc43xx/hackrf-jellybean/ssp/README
+++ b/examples/lpc43xx/hackrf-jellybean/ssp/README
@@ -18,3 +18,31 @@ SSP1_MOSI: Jellybean P9 SPI Pin4
SSP1_SCK: Jellybean P9 SPI Pin2
SSP1_SSEL: Jellybean P9 SPI Pin3
GND: Can be connected to P12 SD Pin1
+
+PCLK clock source is PLL1 288MHz (from IRC 96MHz boot from SPIFI)
+Freq = PCLK / (CPSDVSR * [SCR+1]).
+
+By default (CPSDVSR=0 => Means MAX Divisor)
+SSP1->CR0->SCR = 0x00 => CLK Freq 1.126MHz
+SSP1->CR0->SCR = 0x01 => MOSI Freq 566.9KHz
+...
+
+Test Oscilloscpe:
+SCR=0, CPSDVSR=32 => CLK 9.025MHz
+SCR=1, CPSDVSR=2 => CLK 73MHz
+SCR=2, CPSDVSR=2 => CLK 49MHz
+SCR=4, CPSDVSR=2 => CLK 29MHz
+SCR=8, CPSDVSR=2 => CLK 16MHz
+SCR=16, CPSDVSR=2 => CLK 8.5MHz
+SCR=32, CPSDVSR=2 => CLK 4.386MHz
+SCR=64, CPSDVSR=2 => CLK 2.227MHz
+SCR=1, CPSDVSR=64 => CLK 2.262MHz
+
+Theory:
+SCR=0, CPSDVSR=32 => 288MHz / (32*(0+1) = 9MHz
+SCR=1, CPSDVSR=2 => 288MHz / (2*(1+1) = 72MHz
+SCR=4, CPSDVSR=2 => 288MHz / (2*(4+1) = 28.8MHz
+SCR=32, CPSDVSR=2 => 288MHz / (2*(32+1) = 4.364MHz
+SCR=64, CPSDVSR=2 => 288MHz / (2*(64+1)) = 2.2154MHz
+SCR=128, CPSDVSR=2 => 288MHz / (2*(128+1)) = 1.116MHz
+SCR=1, CPSDVSR=64 => 288MHz / (64*(1+1)) = 2.25MHz
diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c
index 388afc8..cdb3702 100644
--- a/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c
+++ b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c
@@ -26,6 +26,16 @@
void gpio_setup(void)
{
+ /* Configure all GPIO as Input (safe state) */
+ GPIO0_DIR = 0;
+ GPIO1_DIR = 0;
+ GPIO2_DIR = 0;
+ GPIO3_DIR = 0;
+ GPIO4_DIR = 0;
+ GPIO5_DIR = 0;
+ GPIO6_DIR = 0;
+ GPIO7_DIR = 0;
+
/* Configure SCU Pin Mux as GPIO */
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
@@ -44,16 +54,6 @@ void gpio_setup(void)
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
- /* Configure all GPIO as Input (safe state) */
- GPIO0_DIR = 0;
- GPIO1_DIR = 0;
- GPIO2_DIR = 0;
- GPIO3_DIR = 0;
- GPIO4_DIR = 0;
- GPIO5_DIR = 0;
- GPIO6_DIR = 0;
- GPIO7_DIR = 0;
-
/* Configure GPIO as Output */
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
@@ -64,10 +64,12 @@ int main(void)
int i;
u8 ssp_val;
u8 serial_clock_rate;
+ u8 clock_prescale_rate;
gpio_setup();
- /* FIX Me freq */
+ /* Freq About 1.12MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=288MHz */
+ clock_prescale_rate = 2;
serial_clock_rate = 128;
ssp_init(SSP1_NUM,
@@ -75,6 +77,7 @@ int main(void)
SSP_FRAME_SPI,
SSP_CPOL_0_CPHA_0,
serial_clock_rate,
+ clock_prescale_rate,
SSP_MODE_NORMAL,
SSP_MASTER,
SSP_SLAVE_OUT_ENABLE);