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authorUwe Hermann2009-07-22 03:27:01 +0200
committerUwe Hermann2009-07-22 03:27:01 +0200
commitfd1e0290cd90cb5e07820ba5f2a3cdc787a0c8b5 (patch)
treeaadde175e150a789bd4e1ca3e6c259ac133b535d /examples/fancyblink
parent9fd3064cb298124517f2ed1517365175e2c0e6be (diff)
Implement clock_setup() in fancyblink, STM32 should now run at 72 MHz.
Diffstat (limited to 'examples/fancyblink')
-rw-r--r--examples/fancyblink/fancyblink.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/examples/fancyblink/fancyblink.c b/examples/fancyblink/fancyblink.c
index bf8470f..9b0bb07 100644
--- a/examples/fancyblink/fancyblink.c
+++ b/examples/fancyblink/fancyblink.c
@@ -19,10 +19,34 @@
#include <libopenstm32.h>
+void clock_setup(void)
+{
+ /* Select HSI as SYSCLK source. */
+ rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
+
+ /* Set the PLL multiplication factor to 9. */
+ rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
+
+ /* Select HSI/2 as PLL source. */
+ rcc_set_pll_source(PLLSRC_HSI_CLK_DIV2);
+
+ rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
+
+ /* Enable PLL oscillator and wait for it to stabilize. */
+ rcc_osc_on(PLL);
+ rcc_wait_for_osc_ready(PLL);
+
+ /* Select PLL as SYSCLK source. */
+ rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
+}
+
int main(void)
{
int i;
+ /* Set STM32 to 72 MHz. */
+ clock_setup();
+
/* Enable GPIOC clock. */
rcc_enable_peripheral_clock(&RCC_APB2ENR, IOPCEN);