From fd1e0290cd90cb5e07820ba5f2a3cdc787a0c8b5 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Wed, 22 Jul 2009 03:27:01 +0200 Subject: Implement clock_setup() in fancyblink, STM32 should now run at 72 MHz. --- examples/fancyblink/fancyblink.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'examples/fancyblink') diff --git a/examples/fancyblink/fancyblink.c b/examples/fancyblink/fancyblink.c index bf8470f..9b0bb07 100644 --- a/examples/fancyblink/fancyblink.c +++ b/examples/fancyblink/fancyblink.c @@ -19,10 +19,34 @@ #include +void clock_setup(void) +{ + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK); + + /* Set the PLL multiplication factor to 9. */ + rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9); + + /* Select HSI/2 as PLL source. */ + rcc_set_pll_source(PLLSRC_HSI_CLK_DIV2); + + rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK); +} + int main(void) { int i; + /* Set STM32 to 72 MHz. */ + clock_setup(); + /* Enable GPIOC clock. */ rcc_enable_peripheral_clock(&RCC_APB2ENR, IOPCEN); -- cgit v1.2.3