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authorPiotr Esden-Tempski2010-01-16 02:58:19 +0100
committerPiotr Esden-Tempski2010-01-16 04:12:53 +0100
commita38fc2c3a2ae29fe04c352077de45e504a8a3f2e (patch)
tree3f8436dea0a54a5873dfc28d81c143552c4514e5
parent6fe7e25a8a6288639b917f5e6115e8e5d87c1ff1 (diff)
Added basic NVIC register defs and functions.
-rw-r--r--include/libopenstm32.h1
-rw-r--r--include/libopenstm32/memorymap.h37
-rw-r--r--include/libopenstm32/nvic.h116
-rw-r--r--lib/Makefile2
4 files changed, 155 insertions, 1 deletions
diff --git a/include/libopenstm32.h b/include/libopenstm32.h
index 68d4d39..059b6e2 100644
--- a/include/libopenstm32.h
+++ b/include/libopenstm32.h
@@ -32,5 +32,6 @@
#include <libopenstm32/flash.h>
#include <libopenstm32/usb.h>
#include <libopenstm32/usb_desc.h>
+#include <libopenstm32/nvic.h>
#endif
diff --git a/include/libopenstm32/memorymap.h b/include/libopenstm32/memorymap.h
index f364148..a9c7fef 100644
--- a/include/libopenstm32/memorymap.h
+++ b/include/libopenstm32/memorymap.h
@@ -20,6 +20,43 @@
#ifndef LIBOPENSTM32_MEMORYMAP_H
#define LIBOPENSTM32_MEMORYMAP_H
+/* --- ARM Cortex-M3 specific definitions ---------------------------------- */
+
+/* Private peripheral bus - Internal */
+#define PPBI_BASE 0xE0000000
+#define ITM_BASE (PPBI_BASE + 0x0000)
+#define DWT_BASE (PPBI_BASE + 0x1000)
+#define FPB_BASE (PPBI_BASE + 0x2000)
+/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
+#define SCS_BASE (PPBI_BASE + 0xE000)
+/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
+
+/* --- ITM: Instrumentation Trace Macrocell --- */
+/* TODO */
+
+/* --- DWT: Data Watchpoint and Trace unit --- */
+/* TODO */
+
+/* --- FPB: Flash Patch and Breakpoint unit --- */
+/* TODO */
+
+/* --- SCS: System Control Space --- */
+
+/* ITR: Interrupt Type Register */
+#define ITR_BASE (SCS_BASE + 0x0000)
+/* SYS_TICK: System Timer */
+#define SYS_TICK_BASE (SCS_BASE + 0x0010)
+/* NVIC: Nested Vector Interrupt Controller */
+#define NVIC_BASE (SCS_BASE + 0x0100)
+/* SCB: System Control Block */
+#define SCB_BASE (SCS_BASE + 0x0D00)
+/* STE: Software Trigger Interrupt Register */
+#define STIR_BASE (SCS_BASE + 0x0F00)
+/* ID: ID space */
+#define ID_BASE (SCS_BASE + 0x0FD0)
+
+/* --- STM32 specific peripheral definitions ------------------------------- */
+
/* Memory map for all busses */
#define PERIPH_BASE 0x40000000
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
diff --git a/include/libopenstm32/nvic.h b/include/libopenstm32/nvic.h
new file mode 100644
index 0000000..e814e69
--- /dev/null
+++ b/include/libopenstm32/nvic.h
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the libopenstm32 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENSTM32_NVIC_H
+#define LIBOPENSTM32_NVIC_H
+
+#include <libopenstm32.h>
+
+/* --- NVIC Registers ------------------------------------------------------ */
+/* ISER: Interrupt Set Enable Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
+
+/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
+
+/* ICER: Interrupt Clear Enable Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
+
+/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
+
+/* ISPR: Interrupt Set Priority Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
+
+/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
+
+/* ICPR: Interrupt Clear Priority Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
+
+/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
+
+/* IABR: Interrupt Active Bit Register */
+/* Note: 8 32bit Registers */
+#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
+
+/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
+
+/* IPR: Interrupt Priority Registers */
+/* Note: 240 8bit Registers */
+#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
+
+/* STIR: Software Trigger Interrupt Register */
+#define NVIC_STIR MMIO32(STIR_BASE)
+
+/* --- SCB: Registers ------------------------------------------------------ */
+
+/* CPUID: CPUID base register */
+#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
+
+/* ICSR: Interrupt Control State Register */
+#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
+
+/* VTOR: Vector Table Offset Register */
+#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
+
+/* AIRCR: Application Interrupt and Reset Control Register */
+#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
+
+/* SCR: System Control Register */
+#define SCB_SCR MMIO32(SCB_BASE + 0x10)
+
+/* CCR: Configuration Control Register */
+#define SCB_CCR MMIO32(SCB_BASE + 0x14)
+
+/* SHP: System Handler Priority Registers */
+/* Note: 12 8bit registers */
+#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
+
+/* SHCSR: System Handler Control and State Register */
+#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
+
+/* CFSR: Configurable Fault Status Registers */
+#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
+
+/* HFSR: Hard Fault Status Register */
+#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
+
+/* DFSR: Debug Fault Status Register */
+#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
+
+/* MMFAR: Memory Manage Fault Address Register */
+#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
+
+/* BFAR: Bus Fault Address Register */
+#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
+
+/* AFSR: Auxiliary Fault Status Register */
+#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
+
+/* --- NVIC functions ------------------------------------------------------ */
+void nvic_enable_irq(s32 irqn);
+void nvic_disable_irq(s32 irqn);
+s32 nvic_get_pending_irq(s32 irqn);
+void nvic_set_pending_irq(s32 irqn);
+void nvic_clear_pending_irq(s32 irqn);
+s32 nvic_get_active(s32 irqn);
+
+#endif /* LIBOPENSTM32_NVIC_H */
diff --git a/lib/Makefile b/lib/Makefile
index 6cfe4b7..c183967 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -27,7 +27,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../include -fno-common \
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o
+OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o
# Be silent per default, but 'make V=1' will show all compiler calls.
ifneq ($(V),1)