path: root/digital
AgeCommit message (Collapse)Author
2007-08-06Added encoder computations to choose between different decoding solutions.Nicolas Schodet
2007-08-06Added motor models.Nicolas Schodet
2007-08-01Added encoder documentation.Nicolas Schodet
2007-08-01Added xilinx project for CPLD synthesis.Nicolas Schodet
Project fits in a XC9572.
2007-08-01Fixed switch operand sizes in quad_decoder_div4.Nicolas Schodet
Added an output latch, now output will not change when oe is one.
2007-06-30Added hdlcounter for CPLD.Nicolas Schodet
Verilog source files and test cases.