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authorNicolas Schodet2015-08-21 16:28:18 +0200
committerNicolas Schodet2019-10-07 00:44:50 +0200
commitc3f656eb0b9ea146a64b1bdf11c5f3ec5c4e0625 (patch)
tree21b57323e3c3f83e855e55e43a2754cc45d2956c /ucoo
parentd5380c407fb8a563963bf5f7d058f4e90e60cd47 (diff)
ucoo/hal/sdram: new SDRAM module
Diffstat (limited to 'ucoo')
-rw-r--r--ucoo/hal/sdram/Module1
-rw-r--r--ucoo/hal/sdram/sdram.hh33
-rw-r--r--ucoo/hal/sdram/sdram.stm32f4.cc140
-rw-r--r--ucoo/hal/sdram/sdram.stm32f4.hh99
-rw-r--r--ucoo/hal/sdram/test/Makefile9
-rw-r--r--ucoo/hal/sdram/test/test_sdram.stm32f4.cc119
6 files changed, 401 insertions, 0 deletions
diff --git a/ucoo/hal/sdram/Module b/ucoo/hal/sdram/Module
new file mode 100644
index 0000000..8dc6240
--- /dev/null
+++ b/ucoo/hal/sdram/Module
@@ -0,0 +1 @@
+ucoo_hal_sdram_SOURCES := sdram.stm32f4.cc
diff --git a/ucoo/hal/sdram/sdram.hh b/ucoo/hal/sdram/sdram.hh
new file mode 100644
index 0000000..2d1f225
--- /dev/null
+++ b/ucoo/hal/sdram/sdram.hh
@@ -0,0 +1,33 @@
+#ifndef ucoo_hal_sdram_sdram_hh
+#define ucoo_hal_sdram_sdram_hh
+// ucoolib - Microcontroller object oriented library. {{{
+//
+// Copyright (C) 2015 Nicolas Schodet
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+// DEALINGS IN THE SOFTWARE.
+//
+// }}}
+
+#if defined TARGET_stm32f4
+# include "sdram.stm32f4.hh"
+#else
+# error "not implemented for this target"
+#endif
+
+#endif // ucoo_hal_sdram_sdram_hh
diff --git a/ucoo/hal/sdram/sdram.stm32f4.cc b/ucoo/hal/sdram/sdram.stm32f4.cc
new file mode 100644
index 0000000..ed1050c
--- /dev/null
+++ b/ucoo/hal/sdram/sdram.stm32f4.cc
@@ -0,0 +1,140 @@
+// ucoolib - Microcontroller object oriented library. {{{
+//
+// Copyright (C) 2015 Nicolas Schodet
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+// DEALINGS IN THE SOFTWARE.
+//
+// }}}
+#include "ucoo/hal/sdram/sdram.hh"
+#include "ucoo/utils/delay.hh"
+
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/fsmc.h>
+
+namespace ucoo {
+
+Sdram::Sdram (std::initializer_list<Io> ios, const Param &params)
+ : ios_ (ios), params_ (params)
+{
+}
+
+void
+Sdram::enable ()
+{
+ // Setup GPIO, turn controller on.
+ for (auto io : ios_)
+ {
+ gpio_mode_setup (io.gpio, GPIO_MODE_AF, GPIO_PUPD_NONE, io.pins);
+ gpio_set_output_options (io.gpio, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,
+ io.pins);
+ gpio_set_af (io.gpio, GPIO_AF12, io.pins);
+ }
+ rcc_periph_clock_enable (RCC_FSMC);
+ // Prepare SDRAM clock, can only be HCLK/2 or HCLK/3. Can go slower than
+ // requested, but not faster.
+ int clock_div = (rcc_ahb_frequency + params_.clock_hz - 1)
+ / params_.clock_hz;
+ if (clock_div < 2)
+ clock_div = 2;
+ assert (clock_div <= 3);
+ int clock_hz = rcc_ahb_frequency / clock_div;
+ int clock_ns = 1000000000 / clock_hz;
+ // Prepare and set parameters.
+ assert (params_.bank == 1 || params_.bank == 2);
+ assert (params_.cas >= 2 && params_.cas <= 3);
+ assert (params_.banks == 2 || params_.banks == 4);
+ assert (params_.bits == 8 || params_.bits == 16 || params_.bits == 32);
+ assert (params_.row_bits >= 11 && params_.row_bits <= 13);
+ assert (params_.col_bits >= 8 && params_.col_bits <= 11);
+ uint32_t sdcr =
+ FMC_SDCR_RPIPE_NONE
+ | (clock_div == 2 ? FMC_SDCR_SDCLK_2HCLK : FMC_SDCR_SDCLK_3HCLK)
+ | (params_.cas * FMC_SDCR_CAS_SHIFT)
+ | (params_.banks == 2 ? FMC_SDCR_NB2 : FMC_SDCR_NB4)
+ | (params_.bits == 8 ? FMC_SDCR_MWID_8b
+ : (params_.bits == 16 ? FMC_SDCR_MWID_16b : FMC_SDCR_MWID_32b))
+ | ((params_.row_bits - 11) * FMC_SDCR_NR_SHIFT)
+ | ((params_.col_bits - 8) * FMC_SDCR_NC_SHIFT);
+ uint32_t sdtr =
+ ((params_.trcd - 1) * FMC_SDTR_TRCD_SHIFT)
+ | ((params_.trp - 1) * FMC_SDTR_TRP_SHIFT)
+ | ((params_.twr - 1) * FMC_SDTR_TWR_SHIFT)
+ | ((params_.trc - 1) * FMC_SDTR_TRC_SHIFT)
+ | ((params_.tras - 1) * FMC_SDTR_TRAS_SHIFT)
+ | ((params_.txsr - 1) * FMC_SDTR_TXSR_SHIFT)
+ | ((params_.tmrd - 1) * FMC_SDTR_TMRD_SHIFT);
+ if (params_.bank == 1)
+ {
+ FMC_SDCR1 = sdcr;
+ FMC_SDTR1 = sdtr;
+ }
+ else
+ {
+ FMC_SDCR1 = sdcr & FMC_SDCR_DNC_MASK;
+ FMC_SDCR2 = sdcr;
+ FMC_SDTR1 = sdtr & FMC_SDTR_DNC_MASK;
+ FMC_SDTR2 = sdtr;
+ }
+ // Initialise SDRAM.
+ uint32_t bank = params_.bank == 1 ? FMC_SDCMR_CTB1 : FMC_SDCMR_CTB2;
+ while (FMC_SDSR & FMC_SDSR_BUSY)
+ ;
+ FMC_SDCMR = bank | FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
+ delay_us (params_.init_clock_delay_us);
+ while (FMC_SDSR & FMC_SDSR_BUSY)
+ ;
+ FMC_SDCMR = bank | FMC_SDCMR_MODE_PALL;
+ while (FMC_SDSR & FMC_SDSR_BUSY)
+ ;
+ FMC_SDCMR = bank | ((params_.init_auto_refresh - 1)
+ * FMC_SDCMR_NRFS_SHIFT)
+ | FMC_SDCMR_MODE_AUTO_REFRESH;
+ while (FMC_SDSR & FMC_SDSR_BUSY)
+ ;
+ uint32_t sdram_mode =
+ SDRAM_MODE_BURST_LENGTH_1
+ | SDRAM_MODE_BURST_TYPE_SEQUENTIAL
+ | (params_.cas == 2 ? SDRAM_MODE_CAS_LATENCY_2
+ : SDRAM_MODE_CAS_LATENCY_3)
+ | SDRAM_MODE_OPERATING_MODE_STANDARD
+ | SDRAM_MODE_WRITEBURST_MODE_SINGLE;
+ FMC_SDCMR = bank | (sdram_mode * FMC_SDCMR_MRD_SHIFT)
+ | FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
+ // Set refresh rate.
+ int refresh_interval_ns = params_.tref_ms * 1000000
+ / (1 << params_.row_bits);
+ FMC_SDRTR = refresh_interval_ns / clock_ns - 20;
+}
+
+void *
+Sdram::addr () const
+{
+ return params_.bank == 1 ? reinterpret_cast<void *> (FMC_BANK7_BASE)
+ : reinterpret_cast<void *> (FMC_BANK8_BASE);
+}
+
+int
+Sdram::size () const
+{
+ return params_.bits / 8 * (1 << params_.col_bits)
+ * (1 << params_.row_bits) * params_.banks;
+}
+
+} // namespace ucoo
diff --git a/ucoo/hal/sdram/sdram.stm32f4.hh b/ucoo/hal/sdram/sdram.stm32f4.hh
new file mode 100644
index 0000000..fbeefe0
--- /dev/null
+++ b/ucoo/hal/sdram/sdram.stm32f4.hh
@@ -0,0 +1,99 @@
+#ifndef ucoo_hal_sdram_sdram_stm32f4_hh
+#define ucoo_hal_sdram_sdram_stm32f4_hh
+// ucoolib - Microcontroller object oriented library. {{{
+//
+// Copyright (C) 2015 Nicolas Schodet
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+// DEALINGS IN THE SOFTWARE.
+//
+// }}}
+#include "ucoo/common.hh"
+
+#include <initializer_list>
+
+namespace ucoo {
+
+/// Configure an attached SDRAM memory.
+class Sdram
+{
+public:
+ struct Io {
+ uint32_t gpio;
+ uint16_t pins;
+ };
+ struct Param {
+ /// FMC bank connected to SDRAM.
+ int bank;
+ /// Clock frequency.
+ int clock_hz;
+ /// CAS latency (clock cycles).
+ int cas;
+ /// Number of internal banks.
+ int banks;
+ /// Width of data bus.
+ int bits;
+ /// Number of bits in row address.
+ int row_bits;
+ /// Number of bits in column address.
+ int col_bits;
+ /// Row to column delay (clock cycles). Delay between an activate
+ /// command and a read/write.
+ int trcd;
+ /// Row precharge delay (clock cycles). Delay between a precharge
+ /// command and another command.
+ int trp;
+ /// Recovery delay (clock cycles). Delay between a write and a
+ /// precharge command. TWR >= TRAS - TRCD and TWR >= TRC - TRCD -
+ /// TRP.
+ int twr;
+ /// Row cycle delay (clock cycles). Delay between a refresh command
+ /// and an activate command or two consecutive refresh commands.
+ int trc;
+ /// Self refresh time (clock cycles).
+ int tras;
+ /// Exit self refresh delay (clock cycles).
+ int txsr;
+ /// Load mode register to active or refresh delay (clock cycles).
+ int tmrd;
+ /// Refresh period.
+ int tref_ms;
+ /// Delay after clock initialisation.
+ int init_clock_delay_us;
+ /// Number of auto refresh at initialisation.
+ int init_auto_refresh;
+ };
+public:
+ /// Constructor, store parameters.
+ Sdram (std::initializer_list<Io> ios, const Param &params);
+ /// Enable SDRAM controller.
+ void enable ();
+ /// Get base address.
+ void *addr () const;
+ /// Get size.
+ int size () const;
+private:
+ /// GPIO used for SDRAM signals.
+ std::initializer_list<Io> ios_;
+ /// SDRAM parameters.
+ const Param &params_;
+};
+
+} // namespace ucoo
+
+#endif // ucoo_hal_sdram_sdram_stm32f4_hh
diff --git a/ucoo/hal/sdram/test/Makefile b/ucoo/hal/sdram/test/Makefile
new file mode 100644
index 0000000..eb95df4
--- /dev/null
+++ b/ucoo/hal/sdram/test/Makefile
@@ -0,0 +1,9 @@
+BASE = ../../../..
+
+TARGETS = stm32f4
+PROGS = test_sdram
+test_sdram_SOURCES = test_sdram.stm32f4.cc
+
+MODULES = ucoo/hal/gpio ucoo/hal/sdram ucoo/utils ucoo/base/test ucoo/hal/usb
+
+include $(BASE)/build/top.mk
diff --git a/ucoo/hal/sdram/test/test_sdram.stm32f4.cc b/ucoo/hal/sdram/test/test_sdram.stm32f4.cc
new file mode 100644
index 0000000..841d486
--- /dev/null
+++ b/ucoo/hal/sdram/test/test_sdram.stm32f4.cc
@@ -0,0 +1,119 @@
+// ucoolib - Microcontroller object oriented library. {{{
+//
+// Copyright (C) 2015 Nicolas Schodet
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+// DEALINGS IN THE SOFTWARE.
+//
+// }}}
+#include "ucoo/hal/sdram/sdram.hh"
+
+#include "ucoo/arch/arch.hh"
+#include "ucoo/base/test/test.hh"
+
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/stm32/gpio.h>
+
+#include <cstdio>
+#include <cinttypes>
+
+int
+memtest (void *addr, int size, uint32_t pattern)
+{
+ int errors = 0;
+ uint32_t *begin = reinterpret_cast<uint32_t *> (addr);
+ uint32_t *end = begin + size / 4;
+ printf ("memtest %dM, pattern 0x%08" PRIx32 "\n", size / 1024 / 1024, pattern);
+ printf (" fill...\n");
+ for (uint32_t *p = begin; p != end; p++)
+ *p = pattern;
+ printf (" check increasing...\n");
+ for (uint32_t *p = begin; p != end; p++)
+ {
+ if (*p != pattern)
+ errors++;
+ *p = ~pattern;
+ }
+ printf (" check decreasing...\n");
+ for (uint32_t *p = end; p != begin; p--)
+ {
+ if (*(p - 1) != ~pattern)
+ errors++;
+ *(p - 1) = pattern;
+ }
+ printf (" done, %d errors\n", errors);
+ return errors;
+}
+
+int
+main (int argc, const char **argv)
+{
+ ucoo::arch_init (argc, argv);
+ ucoo::test_stream_setup ();
+ rcc_periph_clock_enable (RCC_GPIOD);
+ rcc_periph_clock_enable (RCC_GPIOE);
+ rcc_periph_clock_enable (RCC_GPIOF);
+ rcc_periph_clock_enable (RCC_GPIOG);
+ rcc_periph_clock_enable (RCC_GPIOH);
+ rcc_periph_clock_enable (RCC_GPIOI);
+ std::initializer_list<ucoo::Sdram::Io> sdram_ios {
+ { GPIOD, GPIO0 | GPIO1 | GPIO8 | GPIO9 | GPIO10 | GPIO14 | GPIO15 },
+ { GPIOE, GPIO0 | GPIO1 | GPIO7 | GPIO8 | GPIO9 | GPIO10 | GPIO11
+ | GPIO12 | GPIO13 | GPIO14 | GPIO15 },
+ { GPIOF, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO11
+ | GPIO12 | GPIO13 | GPIO14 | GPIO15 },
+ { GPIOG, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO8
+ | GPIO15 },
+ { GPIOH, GPIO2 | GPIO3 | GPIO5 | GPIO8 | GPIO9 | GPIO10 | GPIO11
+ | GPIO12 | GPIO13 | GPIO14 | GPIO15 },
+ { GPIOI, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO6 | GPIO7
+ | GPIO9 | GPIO10 },
+ };
+ ucoo::Sdram::Param sdram_param {
+ .bank = 1,
+ .clock_hz = 133333333,
+ .cas = 3,
+ .banks = 4,
+ .bits = 32,
+ .row_bits = 12,
+ .col_bits = 8,
+ .trcd = 3,
+ .trp = 3,
+ .twr = 2,
+ .trc = 8,
+ .tras = 6,
+ .txsr = 9,
+ .tmrd = 2,
+ .tref_ms = 64,
+ .init_clock_delay_us = 100,
+ .init_auto_refresh = 2,
+ };
+ ucoo::Sdram sdram (sdram_ios, sdram_param);
+ sdram.enable ();
+ long long errors = 0;
+ for (int i = 0; i < 100; i++)
+ {
+ errors += memtest (sdram.addr (), sdram.size (), 0x00000000);
+ errors += memtest (sdram.addr (), sdram.size (), 0xffffffff);
+ errors += memtest (sdram.addr (), sdram.size (), 0x55aaa55a);
+ errors += memtest (sdram.addr (), sdram.size (), 0xff00ff00);
+ errors += memtest (sdram.addr (), sdram.size (), 0x00ff00ff);
+ printf ("total errors: %lld\n", errors);
+ }
+ return errors == 0 ? 0 : 1;
+}