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authorNicolas Schodet2016-02-09 13:49:04 +0100
committerNicolas Schodet2019-10-07 00:44:57 +0200
commit14d8e68466cdc4fbda3abe5b5cc78ea64a4a8be4 (patch)
tree80112415b8fd2b968361fbe29cb327fce3daa7a2 /ucoo
parent0750809ea4feed01996ff4344047b5eb36a0dfc4 (diff)
ucoo/hal/timer: clear interrupt flag
Diffstat (limited to 'ucoo')
-rw-r--r--ucoo/hal/timer/timer.stm32.hh2
-rw-r--r--ucoo/hal/timer/timer.stm32.tcc7
2 files changed, 9 insertions, 0 deletions
diff --git a/ucoo/hal/timer/timer.stm32.hh b/ucoo/hal/timer/timer.stm32.hh
index f139fce..85941e4 100644
--- a/ucoo/hal/timer/timer.stm32.hh
+++ b/ucoo/hal/timer/timer.stm32.hh
@@ -62,6 +62,8 @@ class TimerHard
void enable_interrupt ();
/// Disable interrupts on update event.
void disable_interrupt ();
+ /// Clear update event interrupt flag.
+ void clear_interrupt ();
private:
/// Enable updates (reload value, output compare values...).
void enable_updates ();
diff --git a/ucoo/hal/timer/timer.stm32.tcc b/ucoo/hal/timer/timer.stm32.tcc
index 4083f26..e95deff 100644
--- a/ucoo/hal/timer/timer.stm32.tcc
+++ b/ucoo/hal/timer/timer.stm32.tcc
@@ -243,6 +243,13 @@ TimerHard<Base>::disable_interrupt ()
template<uint32_t Base>
void
+TimerHard<Base>::clear_interrupt ()
+{
+ TIM_SR (Base) = ~TIM_SR_UIF;
+}
+
+template<uint32_t Base>
+void
TimerHard<Base>::enable_updates ()
{
TIM_CR1 (Base) &= ~TIM_CR1_UDIS;