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authorNicolas Schodet2015-04-29 10:58:15 +0200
committerNicolas Schodet2019-10-07 00:44:50 +0200
commit0ad5dc5b09f749e8d3b1db737d7283ab58412c96 (patch)
tree7c5be2c27af249e5dbaba7ae4c448a9345126f76 /ucoo/hal/i2c/i2c_hard.stm32.cc
parent2b6317815bf86c80047c5d3b42602f81b8c21d01 (diff)
Use new rcc_periph_clock_{enable,disable}
Diffstat (limited to 'ucoo/hal/i2c/i2c_hard.stm32.cc')
-rw-r--r--ucoo/hal/i2c/i2c_hard.stm32.cc15
1 files changed, 7 insertions, 8 deletions
diff --git a/ucoo/hal/i2c/i2c_hard.stm32.cc b/ucoo/hal/i2c/i2c_hard.stm32.cc
index a9e8f00..6cadf8b 100644
--- a/ucoo/hal/i2c/i2c_hard.stm32.cc
+++ b/ucoo/hal/i2c/i2c_hard.stm32.cc
@@ -41,8 +41,8 @@ struct i2c_hardware_t
{
/// I2C base address.
uint32_t base;
- /// RCC enable bit.
- uint32_t rcc_en;
+ /// Clock enable identifier.
+ enum rcc_periph_clken clken;
/// Corresponding event IRQ (error IRQ is next one).
int ev_irq;
};
@@ -51,9 +51,9 @@ struct i2c_hardware_t
/// 0.
static const i2c_hardware_t i2c_hardware[i2c_nb] =
{
- { I2C1_BASE, RCC_APB1ENR_I2C1EN, NVIC_I2C1_EV_IRQ },
- { I2C2_BASE, RCC_APB1ENR_I2C2EN, NVIC_I2C2_EV_IRQ },
- { I2C3_BASE, RCC_APB1ENR_I2C3EN, NVIC_I2C3_EV_IRQ },
+ { I2C1_BASE, RCC_I2C1, NVIC_I2C1_EV_IRQ },
+ { I2C2_BASE, RCC_I2C2, NVIC_I2C2_EV_IRQ },
+ { I2C3_BASE, RCC_I2C3, NVIC_I2C3_EV_IRQ },
};
static I2cHard *i2c_instances[i2c_nb];
@@ -99,7 +99,7 @@ I2cHard::enable (int speed)
enabled_ = true;
uint32_t base = i2c_hardware[n_].base;
// Turn on.
- rcc_peripheral_enable_clock (&RCC_APB1ENR, i2c_hardware[n_].rcc_en);
+ rcc_periph_clock_enable (i2c_hardware[n_].clken);
// Reset.
I2C_CR1 (base) = I2C_CR1_SWRST;
// TODO: make sure the bus is free!!! How!
@@ -145,8 +145,7 @@ I2cHard::disable ()
nvic_disable_irq (i2c_hardware[n_].ev_irq + 1);
I2C_CR1 (base) = 0;
// Turn off.
- rcc_peripheral_disable_clock (&RCC_APB1ENR,
- i2c_hardware[n_].rcc_en);
+ rcc_periph_clock_disable (i2c_hardware[n_].clken);
}
}