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authorNicolas Schodet2016-07-25 15:18:40 +0200
committerNicolas Schodet2019-10-09 23:05:44 +0200
commit4695b47da68a5b2f75270bea21e15b8f1b9fd6ff (patch)
tree6e5ef4d34ee69bcd6c6627f25a0ca3aa902d47e3 /ucoo/arch/interrupt.stm32f4.hh
parentd7df91926bdb529e68eff9a215aef72072803b6e (diff)
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diff --git a/ucoo/arch/interrupt.stm32f4.hh b/ucoo/arch/interrupt.stm32f4.hh
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+++ b/ucoo/arch/interrupt.stm32f4.hh
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+#ifndef ucoo_arch_interrupt_stm32f4_hh
+#define ucoo_arch_interrupt_stm32f4_hh
+// ucoolib - Microcontroller object oriented library. {{{
+//
+// Copyright (C) 2016 Nicolas Schodet
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+// DEALINGS IN THE SOFTWARE.
+//
+// }}}
+
+namespace ucoo {
+
+enum class Irq
+{
+ WWDG,
+ PVD,
+ TAMP_STAMP,
+ RTC_WKUP,
+ FLASH,
+ RCC,
+ EXTI0,
+ EXTI1,
+ EXTI2,
+ EXTI3,
+ EXTI4,
+ DMA1_Stream0,
+ DMA1_Stream1,
+ DMA1_Stream2,
+ DMA1_Stream3,
+ DMA1_Stream4,
+ DMA1_Stream5,
+ DMA1_Stream6,
+ ADC,
+ CAN1_TX,
+ CAN1_RX0,
+ CAN1_RX1,
+ CAN1_SCE,
+ EXTI9_5,
+ TIM1_BRK_TIM9,
+ TIM1_UP_TIM10,
+ TIM1_TRG_COM_TIM11,
+ TIM1_CC,
+ TIM2,
+ TIM3,
+ TIM4,
+ I2C1_EV,
+ I2C1_ER,
+ I2C2_EV,
+ I2C2_ER,
+ SPI1,
+ SPI2,
+ USART1,
+ USART2,
+ USART3,
+ EXTI15_10,
+ RTC_Alarm,
+ OTG_FS_WKUP,
+ TIM8_BRK_TIM12,
+ TIM8_UP_TIM13,
+ TIM8_TRG_COM_TIM14,
+ TIM8_CC,
+ DMA1_Stream7,
+ FMC,
+ SDIO,
+ TIM5,
+ SPI3,
+ UART4,
+ UART5,
+ TIM6_DAC,
+ TIM7,
+ DMA2_Stream0,
+ DMA2_Stream1,
+ DMA2_Stream2,
+ DMA2_Stream3,
+ DMA2_Stream4,
+ ETH,
+ ETH_WKUP,
+ CAN2_TX,
+ CAN2_RX0,
+ CAN2_RX1,
+ CAN2_SCE,
+ OTG_FS,
+ DMA2_Stream5,
+ DMA2_Stream6,
+ DMA2_Stream7,
+ USART6,
+ I2C3_EV,
+ I2C3_ER,
+ OTG_HS_EP1_OUT,
+ OTG_HS_EP1_IN,
+ OTG_HS_WKUP,
+ OTG_HS,
+ DCMI,
+ CRYP,
+ HASH_RNG,
+ FPU,
+ UART7,
+ UART8,
+ SPI4,
+ SPI5,
+ SPI6,
+ SAI1,
+ LTDC,
+ LTDC_ER,
+ DMA2D,
+ COUNT
+};
+
+} // namespace ucoo
+
+#endif // ucoo_arch_interrupt_stm32f4_hh