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authorNicolas Schodet2016-07-25 15:18:40 +0200
committerNicolas Schodet2019-10-09 23:05:44 +0200
commit4695b47da68a5b2f75270bea21e15b8f1b9fd6ff (patch)
tree6e5ef4d34ee69bcd6c6627f25a0ca3aa902d47e3 /ucoo/arch/arch.stm32f4.cc
parentd7df91926bdb529e68eff9a215aef72072803b6e (diff)
Switch to CMSIS
Diffstat (limited to 'ucoo/arch/arch.stm32f4.cc')
-rw-r--r--ucoo/arch/arch.stm32f4.cc16
1 files changed, 10 insertions, 6 deletions
diff --git a/ucoo/arch/arch.stm32f4.cc b/ucoo/arch/arch.stm32f4.cc
index 74c7306..c569c65 100644
--- a/ucoo/arch/arch.stm32f4.cc
+++ b/ucoo/arch/arch.stm32f4.cc
@@ -22,18 +22,22 @@
//
// }}}
#include "ucoo/arch/arch.hh"
-#include "ucoo/common.hh"
-
-#include <libopencm3/stm32/rcc.h>
+#include "ucoo/arch/rcc.stm32.hh"
namespace ucoo {
void
arch_init (int argc, const char **argv)
{
- rcc_clock_setup_hse_3v3 (&hse_8mhz_3v3[CLOCK_3V3_120MHZ]);
- rcc_ahb_frequency = 120000000;
- rcc_periph_clock_enable (RCC_SYSCFG);
+ rcc_sys_clock_setup_pll (120000000, 8000000,
+ 4, // pllm => 8 MHz / 4 = 2 MHz
+ 120, // plln => 2 MHz * 120 = 240 MHz
+ 2, // pllp => 240 MHz / 2 = 120 MHz
+ 5, // pllq => 240 MHz / 5 = 48 MHz
+ 4, // apb1_pre => 30 MHz
+ 2, // apb2_pre => 60 MHz
+ SupplyRange::V2_7);
+ rcc_peripheral_clock_enable (Rcc::SYSCFG);
}
} // namespace ucoo