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-- modele.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Fichier mod�le pour la d�claration de module.

library ieee;
use	ieee.std_logic_1164.all;
use	work.nono_const.all


entity bch_modele is
end bch_modele;

architecture sim1 of bch_modele is
    
    component modele
	generic (
	    -- adresses des diff�rents registres du module.
	    A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION;
	    A_REG2 : T_ADDRESS := A_REG_IO_DATA;
	    A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK
	    -- si autre choses � d�clarer...
	);
	port (
	    rst : in std_logic;
	    clk : in std_logic;
	    rw  : in std_logic; -- read / write
	    bus_data : inout std_logic_vector ((NB_BIT_DATA - 1) downto 0);
	    bus_address : in std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0)
	);
    end modele;

    -- d�finiton des signaux
    signal rst : std_logic;
    signal clk : std_logic;
    signal rw  : std_logic; -- read / write
    signal bus_data : std_logic_vector ((NB_BIT_DATA - 1) downto 0);
    signal bus_address : std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0)

begin
    U1 : modele port map (
	rst => rst,
	clk => clk,
	rw => rw,
	bus_data => bus_data,
	bus_address => bus_address
	);

    rst <= '1', '0' after CK_PERIOD;
    clk <= not clk after CK_PERIOD/2;
    rw <= '0';
    bus_address <=	A_REG_IO_DIRECTION, 
			A_REG_IO_DATA after 3*CK_PERIOD,
			A_REG_IO_INTERRUPT_MASK	after 5*CK_PERIOD;
end sim1;

configuration cf1_bch_modele of bch_modele is
    for sim1
        for all : modele use entity work.modele(test_modele); end for;
    end for;
end cf1_bch_modele;