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Diffstat (limited to '2004/n/fpga/src/three-state/tristate.vhd')
-rw-r--r--2004/n/fpga/src/three-state/tristate.vhd19
1 files changed, 17 insertions, 2 deletions
diff --git a/2004/n/fpga/src/three-state/tristate.vhd b/2004/n/fpga/src/three-state/tristate.vhd
index 07e440e..d3616f7 100644
--- a/2004/n/fpga/src/three-state/tristate.vhd
+++ b/2004/n/fpga/src/three-state/tristate.vhd
@@ -18,6 +18,8 @@ use work.nono_const.all;
entity tristate is
port (
+ rst : std_logic;
+ clk : std_logic;
enable : in std_logic;
data_in : in T_DATA;
data_out : out T_DATA
@@ -26,6 +28,19 @@ end entity;
architecture RTL of tristate is
begin
- -- partie combinatoire.
- data_out <= data_in when (enable = '1') else (others => 'Z');
+ process (rst, clk)
+ begin
+ if (rst = '1') then
+ data_out <= (others => 'Z');
+ elsif (clk'event and clk = '1') then
+ if (enable = '1') then
+ data_out <= data_in;
+ else
+ data_out <= (others => 'Z');
+ end if;
+ end if;
+ end process;
+
+ -- partie combinatoire.
+ --data_out <= data_in when (enable = '1') else (others => 'Z');
end RTL;