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Diffstat (limited to '2004/n/fpga/src/registre/reg_rw.vhd')
-rw-r--r--2004/n/fpga/src/registre/reg_rw.vhd12
1 files changed, 9 insertions, 3 deletions
diff --git a/2004/n/fpga/src/registre/reg_rw.vhd b/2004/n/fpga/src/registre/reg_rw.vhd
index 32e940e..6b1c818 100644
--- a/2004/n/fpga/src/registre/reg_rw.vhd
+++ b/2004/n/fpga/src/registre/reg_rw.vhd
@@ -39,16 +39,22 @@ begin
-- reset
if (rst = '1') then
REG <= (others => '0');
+ data <= (others => 'Z');
-- écriture des données.
- elsif (clk'event and clk = '1') then
+ elsif (clk'event and clk = '1') then
if (enable = '1' and rw = ISA_WRITE) then
REG <= data;
+ else
+ if (enable = '1' and rw = ISA_READ) then
+ data <= REG;
+ else
+ data <= (others =>'Z');
+ end if;
end if;
end if;
- end process;
+ end process;
-- partie combinatoire.
- data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z');
data_out <= REG;
end RTL;