summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/pwm/fsmpwm3.vhd
diff options
context:
space:
mode:
Diffstat (limited to '2004/n/fpga/src/pwm/fsmpwm3.vhd')
-rw-r--r--2004/n/fpga/src/pwm/fsmpwm3.vhd78
1 files changed, 78 insertions, 0 deletions
diff --git a/2004/n/fpga/src/pwm/fsmpwm3.vhd b/2004/n/fpga/src/pwm/fsmpwm3.vhd
new file mode 100644
index 0000000..4776b30
--- /dev/null
+++ b/2004/n/fpga/src/pwm/fsmpwm3.vhd
@@ -0,0 +1,78 @@
+-------------------------------------------------------------------------------
+--fsmpwm3.vhd
+--Eurobot 2004 : APB Team
+--Auteur : Fidèle GAFAN
+--Séquenceur du module générateur des signaux de commande du servo-moteur
+--
+--REMARQUE(S):NADA
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+library work;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+--ENTITY
+
+entity fsmpwm3 is
+port( RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USFSM :in std_logic;
+ tcfsm :in integer range 0 to 20161;--synch des 20 ms
+ enloadfsm :out std_logic
+ );
+end fsmpwm3;
+
+
+--ARCHITECTURE
+architecture BEHAV of fsmpwm3 is
+
+type machine is (STATE1,STATE2, STATE3);
+ signal state_c,state_f : machine;
+begin
+
+ -- PROCESS COMBI
+ process(CLK1USFSM,tcfsm,state_c)
+constant tcmax :integer range 0 to 20161:= 20161;
+ begin
+ enloadfsm <='0';
+ state_f <= state_c;
+ case state_c is
+ when STATE1 => enloadfsm<='0'; --demarrage avec prem valeur de data
+ --sans necessite de load a 1:regdata
+ --sort 0
+ state_f<=STATE3; --passe a st3 dès front de clk1us
+ --pour calculs
+
+ when STATE2 => enloadfsm<='1'; --chargement pendant 1 cycle de
+ --clk1us et tc est max
+ state_f<=STATE3;
+ when STATE3 => enloadfsm<='0'; --calculs
+
+ if (tcfsm=0) then --test de fin de comptage des 20ms
+ state_f<=STATE2;
+ elsif ((tcfsm<=tcmax) and (tcfsm/=0)) then --continuer à compter jusqu'à 20ms
+ state_f<=STATE3;
+ elsif ((tcfsm>tcmax)) then
+ state_f<=STATE2;
+ end if;
+ when others => null;
+
+ end case;
+ end process;
+
+ -- PROCESS SEQ
+ process (RST,CLK)
+ begin
+ if (RST='1') then
+ state_c<=STATE1;
+ --enloadfsm<='0';--si mis, indéterminée !!!
+ elsif (CLK'event and CLK='1') then
+ if (CLK1USFSM='1') then
+ state_c <= state_f;
+ end if;end if;
+ end process;
+
+ end BEHAV;
+