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+-------------------------------------------------------------------------------
+--clk1us.vhd
+--Eurobot 2004 : APB Team
+--Auteur : Fidèle GAFAN
+--Module générateur d'horloge 1us-périodique(0,992us en réalité)
+--
+--REMARQUE(S):changer inc si CLK#32MHz
+--Les calculs ont été faits avec CLK=32MHz
+--donc 31*(1/CLK)=1us
+--d'où inc=31
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+--ENTITY
+entity clk1us is
+ port (
+ RST : in std_logic;
+ CLK : in std_logic; --32MHz
+ CLK1USOUT : out std_logic
+ );
+end entity;
+--ARCHITECTURE
+architecture clk1usbehav of clk1us is
+signal inc : integer range 0 to 31;-- nombres de cycles de clk necessaires
+ --pour 1us decremente
+begin
+ process(RST,CLK)
+ begin
+ if (RST = '1') then
+ CLK1USOUT<='0';
+ inc<=31; --31,25 normalement
+ elsif (CLK'event and CLK = '1') then
+ inc<=((inc)-1);
+ if (inc=30) then
+ CLK1USOUT<='1';
+ else
+ CLK1USOUT<='0';
+ if (inc=0) then
+ inc<=30;
+ end if;
+ end if;
+ end if;
+ end process;
+end clk1usbehav;