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Diffstat (limited to '2004/n/fpga/src/portserie/rxserie/rxserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.vhd13
1 files changed, 7 insertions, 6 deletions
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
index 1ee58ec..e0ec325 100644
--- a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
@@ -46,6 +46,7 @@ entity rxserie is
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA;
clk: in std_logic;
+ clk_ref: in std_logic;
rxin: in std_logic;
irqFIFO: out std_logic;
irqRX: out std_logic;
@@ -110,7 +111,7 @@ end component;
-- signaux
signal rxready:std_logic; -- Receiver data ready to read
-signal rxread:std_logic;
+signal rxread:std_logic:='0';
signal rxparERR:std_logic:='0'; -- Receiver parity error flag
signal rxfrmERR:std_logic:='0'; -- Receiver framing error flag
signal rxovrrERR:std_logic:='0'; -- Receiver overrun error flag
@@ -195,7 +196,7 @@ port map(
-- config
-geneck <= (confreg(4) and clk); -- On/Off et masterck --confreg(4)
+geneck <= (confreg(4) and clk_ref); -- On/Off et clk_ref --confreg(4)
fifopurge<=rst;
-- flags
@@ -208,7 +209,7 @@ flagreg(6) <= rxovrrERR; -- Receiver overrun error flag
-- controle des flux
-fifockout <= (csData and bus_clk and rw and (not rst));
+fifockout <= '1' when (csData='1' and rw='1' and rst='0') else '0';
fifockin <= ((not rxread) and (not fifoFull));
inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z');
@@ -216,9 +217,9 @@ inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z');
bus_data <= inter_bus;
-- irq
-irqFifo <= (fifoLevel(1) and fifoLevel(0)) and confreg(2); --fifo almost full AND Int/En
-irqRx <= (not fifoEmpty) and confreg(3);
-irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull) and confreg(5);
+irqFifo <= (fifoLevel(1) and fifoLevel(0));-- and confreg(2); --fifo almost full AND Int/En
+irqRx <= (not fifoEmpty);-- and confreg(3);
+irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull);-- and confreg(5);
-- sortie de donnée du récepteur
process(rxck)