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Diffstat (limited to '2004/n/fpga/src/portserie/rxserie/rxserie.npl')
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.npl14
1 files changed, 12 insertions, 2 deletions
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.npl b/2004/n/fpga/src/portserie/rxserie/rxserie.npl
index 597ac7c..a400a08 100644
--- a/2004/n/fpga/src/portserie/rxserie/rxserie.npl
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.npl
@@ -29,10 +29,20 @@ SOURCE sfifo.xco
STIMULUS bch_rxserie.vhd
SOURCE ..\..\modele\nono_const.vhd
SOURCE ..\..\modele\isa_const.vhd
+STIMULUS ..\..\registre\test_reg.vhd
[Normal]
+p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079483024, D:\xilinx\vhdl\src
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1079088462, ModelSim SE
+p_ModelSimListWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimProcWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimSimRunTime_tb=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1080007098, 1000us
+p_ModelSimSourceWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimUutInstName_postPar=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1079653969, UUT
+p_ModelSimVarsWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+_VhdlSimDo_post=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079736489, True
[STATUS-ALL]
-rxserie.ngcFile=WARNINGS,1079226990
-rxserie.ngdFile=WARNINGS,1079300826
+rxserie.ngcFile=WARNINGS,1080007519
+rxserie.ngdFile=WARNINGS,1080007524
+rxserie.postMapVHDLSimModel=WARNINGS,1080007527
[STRATEGY-LIST]
Normal=True