summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/portserie/portserie/txserie.vhd
diff options
context:
space:
mode:
Diffstat (limited to '2004/n/fpga/src/portserie/portserie/txserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/portserie/txserie.vhd21
1 files changed, 14 insertions, 7 deletions
diff --git a/2004/n/fpga/src/portserie/portserie/txserie.vhd b/2004/n/fpga/src/portserie/portserie/txserie.vhd
index b1ceb53..2b94529 100644
--- a/2004/n/fpga/src/portserie/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/portserie/txserie.vhd
@@ -46,6 +46,7 @@ entity txserie is
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA:=(others => 'Z');
clk: in std_logic;
+ clk_ref: in std_logic;
txout: out std_logic;
minIRQ: out std_logic;
csData : in std_logic;
@@ -115,16 +116,15 @@ signal txck: std_logic;
signal geneck:std_logic;
signal txload: std_logic:='0';
-signal loadingtx: std_logic:='0';
signal confreg: T_DATA:="00000000";
signal flagreg: T_DATA:="00000000";
signal inter_data: T_DATA;
-signal inter_fifo_bus: T_DATA;
+--signal inter_fifo_bus: T_DATA;
signal txready: std_logic:='1';
signal fifodready :std_logic;
-signal state:integer:=1;
-signal state_next:integer:=1;
+--signal state:integer:=1;
+--signal state_next:integer:=1;
signal state_txload:integer:=0;
signal dummy : T_DATA :=(others =>'0');
@@ -135,7 +135,7 @@ signal un: std_logic :='1';
begin
CLOCK1 : clockgene port map(
rst => rst,
- ckin=>geneck,
+ ckin=>clk_ref,--geneck,
ckout=>txck,
param=>confreg(1 downto 0));
@@ -185,7 +185,7 @@ RFLAG : regIO port map(
-- signaux
-- config
-geneck <= (confreg(4) and clk); -- On/Off et masterck
+geneck <= (clk_ref);-- and confreg(4); -- On/Off et masterck
fifopurge <= '1' when (rst='1') else confreg(3); -- reset or purge
-- flags
@@ -208,22 +208,29 @@ begin
state_txload <= 3;
elsif(fifodready='1') then
state_txload <= 1;
+ else
+ state_txload <= 0;
end if;
when 1 => if(txready='1') then
state_txload <= 2;
txload <= '1';
+ else
+ state_txload <= 1;
end if;
when 2 => if(txready='0') then
state_txload <= 0;
else
txload <= '1';
+ state_txload <= 2;
end if;
when 3 => if(fifodready='1') then
state_txload <= 2;
txload <= '1';
+ else
+ state_txload <= 3;
end if;
- when others => null;
+ when others => state_txload <= 0;
end case;
end process;