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Diffstat (limited to '2004/n/fpga/src/portserie/portserie/bch_txserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/portserie/bch_txserie.vhd12
1 files changed, 8 insertions, 4 deletions
diff --git a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
index 3400854..25fadff 100644
--- a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
+++ b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
@@ -22,6 +22,7 @@ component txserie
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA:=(others => 'Z');
clk: in std_logic;
+ clk_ref: in std_logic;
txout: out std_logic;
minIRQ: out std_logic;
csData : in std_logic;
@@ -35,6 +36,7 @@ end component;
signal simclk:std_logic:='0';
signal rst : std_logic;
signal clk : std_logic;
+signal clk_ref : std_logic:='0';
signal rw : std_logic;
signal bus_data : T_DATA:=(others => 'Z');
signal masterck: std_logic:='0';
@@ -44,18 +46,19 @@ signal csData : std_logic;
signal csConfig : std_logic;
signal csFlag : std_logic;
-signal state:integer:=-3;
+signal state:integer:=-30;
begin
- U1 : txserie
+ UUT : txserie
port map(
rst => rst,
bus_clk => clk,
rw =>rw,
bus_data => bus_data,
clk => masterck,
+ clk_ref => clk_ref,
txout => txout,
minIRQ => minirq,
csData => csData,
@@ -66,6 +69,7 @@ begin
rst<='1','0' after 5 ns;
simclk<= not simclk after 10 ns;
masterck<= not masterck after 3 ns;
+ clk_ref <= not clk_ref after 10 ns;
combi:process(state)
begin
@@ -77,10 +81,10 @@ begin
csFlag <= '0';
case state is
- when 1 => bus_data<="00010110";
+ when 1 => bus_data<="01110111";
csConfig<='1';
rw<='0';
- when 2 => bus_data<="00010110";
+ when 2 => bus_data<="01110111";
csConfig<='1';
rw<='0';
clk<='1';