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Diffstat (limited to '2004/n/fpga/src/portserie/clockgene/clockgene.vhd')
-rw-r--r--2004/n/fpga/src/portserie/clockgene/clockgene.vhd16
1 files changed, 7 insertions, 9 deletions
diff --git a/2004/n/fpga/src/portserie/clockgene/clockgene.vhd b/2004/n/fpga/src/portserie/clockgene/clockgene.vhd
index b98a6b3..554d561 100644
--- a/2004/n/fpga/src/portserie/clockgene/clockgene.vhd
+++ b/2004/n/fpga/src/portserie/clockgene/clockgene.vhd
@@ -9,8 +9,7 @@
library ieee;
use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
use work.nono_const.all;
-- pour la valeur de DIVIS_CK_SERIAL
@@ -31,9 +30,8 @@ port(
);
end clockgene;
-
architecture rtl of clockgene is
-signal compteur:std_logic_vector(10 downto 0):=(others=>'0');
+signal compteur:std_logic_vector(9 downto 0):="0000000000";
signal div_param:integer; -- le diviseur paramétrable
signal clr:std_logic;
@@ -48,7 +46,7 @@ begin
when "01" => div_param <= (DIVIS_CK_SERIAL*6); -- 19200 * 6 =115200
when "10" => div_param <= (DIVIS_CK_SERIAL*2); -- 57600 * 2 =115200
when "11" => div_param <= DIVIS_CK_SERIAL; -- 115200 * 1=115200
- when others => null;
+ when others => div_param <= (DIVIS_CK_SERIAL*12); -- 9600 * 12 =115200
end case;
end process;
@@ -57,13 +55,13 @@ begin
begin
if(clr='1') then
ckout<='0';
- compteur<=(others=>'0');
+ compteur<=conv_std_logic_vector(div_param, 10);
elsif(ckin'event and ckin='1') then
- if(compteur = div_param) then
+ if(compteur = "0000000000") then
ckout<='1';
- compteur<=(others=>'0');
+ compteur<=conv_std_logic_vector(div_param, 10);
else
- compteur <= compteur + 1;
+ compteur <= conv_std_logic_vector( (unsigned(compteur) - 1),10);
ckout<='0';
end if;
end if;