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Diffstat (limited to '2004/n/fpga/src/gpio/bch_reg_rw.vhd')
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diff --git a/2004/n/fpga/src/gpio/bch_reg_rw.vhd b/2004/n/fpga/src/gpio/bch_reg_rw.vhd
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+-- bch_reg_rw.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Test de reg_rw.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.isa_const.all;
+use work.nono_const.all;
+
+
+entity bch_reg_rw is
+end bch_reg_rw;
+
+architecture sim1 of bch_reg_rw is
+
+ component reg_rw
+ port (
+ rst : in std_logic;
+ rw : in std_logic;
+ enable : in std_logic;
+ data_in : inout T_DATA;
+ data_out : out T_DATA
+ );
+ end component;
+
+ -- définiton des signaux
+ signal rst : std_logic;
+ signal rw : std_logic; -- read / write
+ signal enable : std_logic;
+ signal data_in : T_DATA;
+ signal data_out : T_DATA;
+
+begin
+ U1 : reg_rw port map (
+ rst => rst,
+ rw => rw,
+ enable => enable,
+ data_in => data_in,
+ data_out => data_out
+ );
+
+ rst <= '1', '0' after CK_PERIOD;
+ enable <= '0',
+ '1' after 2*CK_PERIOD,
+ '0' after 3*CK_PERIOD,
+ '1' after 5*CK_PERIOD,
+ '0' after 6*CK_PERIOD;
+ rw <= '1', '0' after 3*CK_PERIOD;
+ data_in <= x"01",
+ x"02" after 3*CK_PERIOD,
+ "ZZZZZZZZ" after 5*CK_PERIOD;
+ --x"03" after 5*CK_PERIOD;
+end sim1;
+
+configuration cf1_bch_reg_rw of bch_reg_rw is
+ for sim1
+ for all : reg_rw use entity work.reg_rw(BEHAV); end for;
+ end for;
+end cf1_bch_reg_rw;
+